ETHER-1GQD-O4-B1 Lattice

TM ispLever CORECORE 10/100 and 1Gig Ethernet Media Access Controller Users Guide March 2006 ipug09_05.0 10/100 and 1Gig Ethernet Lattice Semiconductor Media Access Controller Users Guide Introduction This document serves as a guide containing technical information about the Lattice 10/100 and 1Gig Ethernet Media Access Controller (MAC) IP cores. The 10/100 and 1Gig Ethernet MAC cores come with the following documentation and les: Data sheet Protected netlist/database Protected RTL simulation model Source les for instantiating the core Core Specication Features Compliant to IEEE 802.3z Standard Generic Host Interface Congurable 8-bit or 16-bit Data Bus Widths 16-bit Wide Internal Data Path Generic Transmit and Receive FIFO Interface Full-duplex Operation in Gigabit Mode Full- and Half-duplex in 10/100 Mode Transmit and Receive Statistics Vector Programmable Inter Packet Gap (IPG) Multicast Address Filtering Supports Full-duplex Control Using PAUSE Frames VLAN Tagged Frames Automatic Re-transmission on Collision Automatic Padding of Short Frames Multicast and Broadcast Frames Optional FCS Transmission and Reception Optional MII Management Interface Module Supports Jumbo Frames up to 8192 kbytes Reference Design for GMII to RGMII Bridge Reduced pin count Gigabit Media Independent Interface General Description The Ethernet Media Access Controller (MAC) core can be congured to operate in either the Gigabit mode (1000 Mbits/sec data rate) or the Fast Ethernet mode (10/100 Mbits/sec data rate). Netlist congurations of this core operate only in either the Gigabit mode or Fast Ethernet mode. The netlist cannot auto-negotiate between the two different modes. The Ethernet MAC transmits and receives data between a host processor and an Ethernet network. The main func- tion of the Ethernet MAC is to ensure that the Media Access rules specied in the 802.3 IEEE standard are met while transmitting a frame of data over Ethernet. Figure 2 shows the transmission of data on the Ethernet network 2