ispLSI 1048C Device Datasheet September 2010 All Devices Discontinued Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line Ordering Part Number Product Status Reference PCN ispLSI 1048C-50LQ ispLSI 1048C-70LQ PCN 13-10 ispLSI 1048C ispLSI 1048C-50LQI Discontinued ispLSI 1048C-50LG/883 PCN 05A-10 5962-9558701MXC 5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Phone (503) 268-8000 FAX (503) 268-8347 Internet: ispLSI 1048C In-System Programmable High Density PLD Features Functional Block Diagram HIGH-DENSITY PROGRAMMABLE LOGIC Output Routing Pool Output Routing Pool 8000 PLD Gates F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output Enables A0 D7 DQ A1 D6 288 Registers A2 D5 High-Speed Global Interconnect DQ Logic A3 D4 Wide Input Gating for Fast Counters, State Global Routing Pool (GRP) GLB Array DQ A4 D3 Machines, Address Decoders, etc. A5 D2 Small Logic Block Size for Random Logic DQ A6 D1 Security Cell Prevents Unauthorized Copying A7 D0 2 HIGH PERFORMANCE E CMOS TECHNOLOGY B0 B1 B2 B3 B4 B5 B6 B7 C0 C1 C2 C3 C4 C5 C6 C7 CLK fmax = 70 MHz Maximum Operating Frequency Output Routing Pool Output Routing Pool fmax = 50 MHz for Industrial and Military/883 Devices tpd = 16 ns Propagation Delay 0139G1A-isp TTL Compatible Inputs and Outputs Electrically Erasable and Reprogrammable 2 Description Non-Volatile E CMOS Technology 100% Tested at Time of Manufacture The ispLSI 1048C is a High-Density Programmable Logic IN-SYSTEM PROGRAMMABLE Device containing 288 Registers, 96 Universal I/O pins, In-System Programmable (ISP) 5-Volt Only 12 Dedicated Input pins, two Global Output Enables Increased Manufacturing Yields, Reduced Time-to- Market, and Improved Product Quality (GOE), four Dedicated Clock Input pins and a Global Reprogram Soldered Devices for Faster Debugging Routing Pool (GRP). The GRP provides complete COMBINES EASE OF USE AND THE FAST SYSTEM interconnectivity between all of these elements. The SPEED OF PLDs WITH THE DENSITY AND FLEX- ispLSI 1048C features 5-Volt in-system programming IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS and in-system diagnostic capabilities. It is the first device Complete Programmable Device Can Combine Glue which offers non-volatile reprogrammability of the logic, Logic and Structured Designs and the interconnect to provide truly reconfigurable sys- Four Dedicated Clock Input Pins tems. Compared to the ispLSI 1048, the ispLSI 1048C Synchronous and Asynchronous Clocks offers two additional dedicated inputs and two new Glo- Flexible Pin Placement bal Output Enable pins. Optimized Global Routing Pool Provides Global Interconnectivity The basic unit of logic on the ispLSI 1048C device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. F7 in figure 1. There are a total of 48 GLBs in the ispLSI 1048C devices. Each GLB has 18 inputs, a program- mable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. January 2002 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556