Product Information

ISPLSI 2064VE-100LTN100

ISPLSI 2064VE-100LTN100 electronic component of Lattice

Datasheet
CPLD ispLSI® 2000VE Family 2K Gates 64 Macro Cells 100MHz 3.3V 100-Pin TQFP

Manufacturer: Lattice
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

7: USD 12.1556 ea
Line Total: USD 85.0892

16745 - Global Stock
Ships to you between
Thu. 04 Apr to Wed. 10 Apr
MOQ: 7  Multiples: 1
Pack Size: 1
Availability Price Quantity
16723 - Global Stock


Ships to you between Thu. 04 Apr to Wed. 10 Apr

MOQ : 5001
Multiples : 1
5001 : USD 3.875
10000 : USD 3.7375

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Number of Macrocells
Maximum Operating Frequency
Delay Time
Operating Supply Voltage
Maximum Operating Temperature
Mounting Style
Brand
Number Of Usable Gates
Operating Temp Range
Pin Count
Operating Temperature Classification
Family Name
Package Type
I/Os Max
Number Of Logic Blocks/Elements
Memory Type
Rad Hardened
In System Programmable
Operating Supply Voltage Max
Programmable
LoadingGif

Notes:- Show Stocked Products With Similar Attributes.
Image Description
ICE40HX8K-B-EVN electronic component of Lattice ICE40HX8K-B-EVN

Programmable Logic IC Development Tools iCE40HX8K Breakout Board
Stock : 3

ICE5LP2K-SWG36ITR50 electronic component of Lattice ICE5LP2K-SWG36ITR50

iCE40 Ultra™ Field Programmable Gate Array (FPGA) IC 26 81920 2048 36-XFBGA, WLCSP
Stock : 0

ICE40LM4K-S-EVN electronic component of Lattice ICE40LM4K-S-EVN

Programmable Logic IC Development Tools ICE40LM4K Sensor Evaluation Kit
Stock : 1

ICE40LP8K-USBC-EVN electronic component of Lattice ICE40LP8K-USBC-EVN

Programmable Logic IC Development Tools iCE40LP8K USB Type-C Demo Kit V2
Stock : 0

ispPAC-POWR6AT6-01SN32I electronic component of Lattice ispPAC-POWR6AT6-01SN32I

Power Supply Controller Power Supply Controller/Monitor 32-QFNS (5x5)
Stock : 0

ISPLSI 2192VE-100LB144ADN electronic component of Lattice ISPLSI 2192VE-100LB144ADN

CPLD ispLSI 2000VE Family 8K Gates 192 Macro Cells 100MHz 3.3V
Stock : 0

ISPLSI 5256VE-100LF256 electronic component of Lattice ISPLSI 5256VE-100LF256

IPL5256VE / USE ISPMACH 4000V
Stock : 0

ISPLSI 2032A-80LJ44 electronic component of Lattice ISPLSI 2032A-80LJ44

32 MC, 32 I/O, ISP, 5V / USE I
Stock : 1

LC4032ZC-75T48E electronic component of Lattice LC4032ZC-75T48E

CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD
Stock : 0

HDMI-VIP-IB-EVN electronic component of Lattice HDMI-VIP-IB-EVN

Interface Development Tools HDMI VIP Input Bridge Board
Stock : 13

Image Description
LC4256ZC-75TN176C electronic component of Lattice LC4256ZC-75TN176C

CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD
Stock : 2

EPM7032LC44 electronic component of Intel EPM7032LC44

EPM7032LC44-10 INTEG CCT EPLD -10 T/HOLE
Stock : 0

EPM7064SLC84-10 electronic component of Intel EPM7064SLC84-10

CPLD - Complex Programmable Logic Devices CPLD - MAX 7000 64 Macro 68 IOs
Stock : 1

LC4064C-5TN100C electronic component of Lattice LC4064C-5TN100C

CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD
Stock : 0

LC4032ZC-75T48E electronic component of Lattice LC4032ZC-75T48E

CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD
Stock : 0

XC95288XL-7FG256I electronic component of Xilinx XC95288XL-7FG256I

CPLD XC9500XL Family 6.4K Gates 288 Macro Cells 125MHz 0.35um (CMOS) Technology 3.3V 256-Pin FBGA
Stock : 0

ATF1504ASV-15JU44 electronic component of Microchip ATF1504ASV-15JU44

CPLD - Complex Programmable Logic Devices CPLD 64 MACROCELL w/ ISP STD PWR 3.3V
Stock : 785

XC9572XL-7TQG100I electronic component of Xilinx XC9572XL-7TQG100I

CPLD, 72 I/O, -40 TO 85DEG C; CPLD Type:FLASH; No. of Macrocells:72; No. of I/O's:72I/O's; Logic Case Style:TQFP; No. of Pins:100Pins; Frequency:125MHz; Supply Voltage Min:3V; Supply Voltage Max:3.6V; Propagation Delay:7.5ns; Global Clock Setup Time:4.8ns; Operating Temperature Min:-40C; Operating Temperature Max:85C; Product Range:XC9572XL Series; SVHC:No SVHC (27-Jun-2018)
Stock : 0

EPM3128ATC144-10 electronic component of Intel EPM3128ATC144-10

CPLD MAX 3000A Family 2.5K Gates 128 Macro Cells 98MHz 3.3V 144-Pin TQFP Tray
Stock : 1

EPM7128AETC144-10 electronic component of Intel EPM7128AETC144-10

CPLD MAX 7000A Family 2.5K Gates 128 Macro Cells 98MHz 3.3V 144-Pin TQFP Tray
Stock : 1

ispLSI 2064VE 3.3V In-System Programmable High Density SuperFAST PLD Features Functional Block Diagram SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC 2000 PLD Gates Input Bus 64 and 32 I/O Pin Versions, Four Dedicated Inputs Output Routing Pool (ORP) 64 Registers B7 B6 B5 B4 High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Global Routing Pool A0 B3 (GRP) Small Logic Block Size for Random Logic 100% Functional, JEDEC and Pinout Compatible with A1 DQ B2 ispLSI 2064V Devices DQ Logic 3.3V LOW VOLTAGE 2064 ARCHITECTURE GLB Array DQ B1 A2 Interfaces with Standard 5V TTL Devices DQ 2 HIGH-PERFORMANCE E CMOS TECHNOLOGY A3 B0 fmax = 280MHz Maximum Operating Frequency tpd = 3.5ns Propagation Delay A4 A5 A6 A7 Electrically Erasable and Reprogrammable Output Routing Pool (ORP) Non-Volatile Input Bus 100% Tested at Time of Manufacture Unused Product Term Shutdown Saves Power 0139A/2064V IN-SYSTEM PROGRAMMABLE Description 3.3V In-System Programmability (ISP) Using Boundary Scan Test Access Port (TAP) The ispLSI 2064VE is a High Density Programmable Open-Drain Output Option for Flexible Bus Interface Logic Device available in 64 and 32 I/O-pin versions. The Capability, Allowing Easy Implementation of Wired-OR device contains 64 Registers, four Dedicated Input pins, or Bus Arbitration Logic three Dedicated Clock Input pins, two dedicated Global Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality OE input pins and a Global Routing Pool (GRP). The Reprogram Soldered Devices for Faster Prototyping GRP provides complete interconnectivity between all of these elements. The ispLSI 2064VE features in-system 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE programmability through the Boundary Scan Test Ac- THE EASE OF USE AND FAST SYSTEM SPEED OF cess Port (TAP) and is 100% IEEE 1149.1 Boundary PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs Scan Testable. The ispLSI 2064VE offers non-volatile Enhanced Pin Locking Capability reprogrammability of the logic, as well as the intercon- Three Dedicated Clock Input Pins nect, to provide truly reconfigurable systems. Synchronous and Asynchronous Clocks Programmable Output Slew Rate Control The basic unit of logic on the ispLSI 2064VE device is the Flexible Pin Placement Generic Logic Block (GLB). The GLBs are labeled A0, Optimized Global Routing Pool Provides Global A1B7 (see Figure 1). There are a total of 16 GLBs in the Interconnectivity ispLSI 2064VE device. Each GLB is made up of four LEAD-FREE PACKAGE OPTIONS macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2004 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556 Specifications ispLSI 2064VE Functional Block Diagram Figure 1. ispLSI 2064VE Functional Block Diagram (64-I/O and 32-I/O Versions) Generic Logic Generic Logic Input Bus Input Bus Blocks (GLBs) Blocks (GLBs) Output Routing Pool (ORP) Output Routing Pool (ORP) Megablock Megablock B7 B6 B5 B4 B7 B6 B5 B4 I/O 47 I/O 0 I/O 23 I/O 0 I/O 1 A0 B3 I/O 46 I/O 1 I/O 22 A0 B3 I/O 2 I/O 45 I/O 2 I/O 21 I/O 3 I/O 44 I/O 3 I/O 20 I/O 4 I/O 43 I/O 5 I/O 42 Global Routing Pool A1 B2 Global Routing Pool I/O 6 A1 B2 I/O 41 (GRP) (GRP) I/O 7 I/O 40 I/O 8 I/O 39 I/O 9 I/O 38 A2 I/O 10 B1 I/O 37 A2 B1 I/O 11 I/O 36 I/O 12 I/O 35 I/O 4 I/O 19 I/O 13 I/O 34 I/O 5 I/O 18 I/O 14 I/O 33 I/O 6 I/O 17 A3 B0 A3 B0 I/O 15 I/O 32 I/O 7 I/O 16 GOE0/IN 3 TCK/IN 3 TDI/IN 0 TDI/IN 0 A4 A5 A6 A7 A4 A5 A6 A7 TMS/IN 2 TMS/IN 1 TDO/IN 2 TDO/IN 1 Output Routing Pool (ORP) RESET Output Routing Pool (ORP) BSCAN Input Bus BSCAN Input Bus 0139B/2064VE 0139B/2064VE.32IO The 64-I/O 2064VE contains 64 I/O cells, while the 32- Y1, Y2) or an asynchronous clock can be selected on a I/O version contains 32 I/O cells. Each I/O cell is directly GLB basis. The asynchronous or Product Term clock connected to an I/O pin and can be individually pro- can be generated in any GLB for its own clock. grammed to be a combinatorial input, output or Programmable Open-Drain Outputs bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers In addition to the standard output configuration, the can source 4 mA or sink 8 mA. Each output can be outputs of the ispLSI 2064VE are individually program- programmed independently for fast or slow output slew mable, either as a standard totem-pole output or an rate to minimize overall output switching noise. Device open-drain output. The totem-pole output drives the pins can be safely driven to 5-Volt signal levels to support specified Voh and Vol levels, whereas the open-drain mixed-voltage systems. output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and pull-up. This output configuration is controlled by a pro- two or one ORPs are connected together to make a grammable fuse. The default configuration when the Megablock (see Figure 1). The outputs of the eight GLBs device is in bulk erased state is totem-pole configuration. are connected to a set of 32 or 16 universal I/O cells by The open-drain/totem-pole option is selectable through two or one ORPs. Each ispLSI 2064VE device contains the Lattice software tools. two Megablocks. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 2064VE device are selected using the dedicated clock pins. Three dedicated clock pins (Y0, 2 GOE 0 Input Bus GOE 1 Output Routing Pool (ORP) I/O 16 I/O 17 I/O 18 I/O 19 I/O 63 I/O 20 I/O 62 I/O 21 I/O 61 I/O 22 I/O 60 I/O 23 I/O 59 I/O 24 I/O 58 I/O 25 I/O 57 I/O 26 I/O 56 I/O 27 I/O 55 I/O 28 I/O 54 I/O 29 I/O 53 I/O 30 I/O 52 I/O 31 I/O 51 I/O 50 I/O 49 I/O 48 CLK 0 Y0 CLK 1 Y1 CLK 2 Y2 Output Routing Pool (ORP) Input Bus Input Bus Output Routing Pool (ORP) I/O 8 I/O 9 I/O 10 I/O 11 I/O 31 I/O 30 I/O 29 I/O 28 I/O 12 I/O 13 I/O 14 I/O 15 I/O 27 I/O 26 I/O 25 I/O 24 CLK 0 GOE1/Y0 CLK 1 RESET/Y1 CLK 2 TCK/Y2 Output Routing Pool (ORP) Input Bus

Tariff Desc

8542.31.00 51 No ..Application Specific (Digital) Integrated Circuits (ASIC)

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Monolithic integrated circuits:
LA4
LAT
LATTICE SEMI
Lattice Semiconductor
Lattice Semiconductor Corporation
Vantis

Looking for help? Visit our FAQ's Section to answer to all your questions

 

X-ON Worldwide Electronics

Welcome To X-ON ELECTRONICS
For over three decades, we have been advocating and shaping the electronic components industry. Our management complements our worldwide business scope and focus. We are committed to innovation, backed by a strong business foundation. If you need a trustworthy supplier of electronic components for your business – look no further.
 

Copyright ©2024  X-ON Electronic Services. All rights reserved.
Please ensure you have read and understood our Terms & Conditions before purchasing.
All prices exclude GST.

Image for all the cards that are accepted Image for all the cards that are accepted Image for all the cards that are accepted Image for all the cards that are accepted Image for all the cards that are accepted