Select devices have been discontinued. See Ordering Information section for product status. ispLSI 2096/A In-System Programmable High Density PLD Features Functional Block Diagram ENHANCEMENTS ispLSI 2096A is Fully Form and Function Compatible Output Routing Pool (ORP) Output Routing Pool (ORP) to the ispLSI 2096, with Identical Timing C7 C6 C5 C4 C3 C2 C1 C0 Specifcations and Packaging A0 B7 ispLSI 2096A is Built on an Advanced 0.35 Micron 2 DQ CMOS Technology E A1 B6 DQ Logic HIGH DENSITY PROGRAMMABLE LOGIC Global Routing Pool Array DQ GLB (GRP) A2 B5 4000 PLD Gates DQ 96 I/O Pins, Six Dedicated Inputs A3 B4 96 Registers High Speed Global Interconnect A4 A5 A6 A7 B0 B1 B2 B3 Wide Input Gating for Fast Counters, State Output Routing Pool (ORP) Output Routing Pool (ORP) Machines, Address Decoders, etc. Small Logic Block Size for Random Logic 0919/2096 2 HIGH PERFORMANCE E CMOS TECHNOLOGY Description fmax = 125 MHz Maximum Operating Frequency The ispLSI 2096 and 2096A are High Density Program- tpd = 7.5 ns Propagation Delay mable Logic Devices. The devices contain 96 Registers, TTL Compatible Inputs and Outputs 96 Universal I/O pins, six Dedicated Input pins, three Electrically Erasable and Reprogrammable Dedicated Clock Input pins, two dedicated Global OE Non-Volatile 100% Tested at Time of Manufacture input pins and a Global Routing Pool (GRP). The GRP Unused Product Term Shutdown Saves Power provides complete interconnectivity between all of these elements. The ispLSI 2096 and 2096A feature 5V in- IN-SYSTEM PROGRAMMABLE system programmability and in-system diagnostic In-System Programmable (ISP) 5V Only capabilities. The ispLSI 2096 and 2096A offer non- Increased Manufacturing Yields, Reduced Time-to- volatile reprogrammability of the logic, as well as the Market and Improved Product Quality Reprogram Soldered Devices for Faster Prototyping interconnect to provide truly reconfigurable systems. OFFERS THE EASE OF USE AND FAST SYSTEM The basic unit of logic on these devices is the Generic SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY Logic Block (GLB). The GLBs are labeled A0, A1C7 OF FIELD PROGRAMMABLE GATE ARRAYS (Figure 1). There are a total of 24 GLBs in the ispLSI 2096 Complete Programmable Device Can Combine and 2096A devices. Each GLB is made up of four Glue Logic and Structured Designs macrocells. Each GLB has 18 inputs, a programmable Enhanced Pin Locking Capability AND/OR/Exclusive OR array, and four outputs which can Three Dedicated Clock Input Pins be configured to be either combinatorial or registered. Synchronous and Asynchronous Clocks Inputs to the GLB come from the GRP and dedicated Programmable Output Slew Rate Control to Minimize Switching Noise inputs. All of the GLB outputs are brought back into the Flexible Pin Placement GRP so that they can be connected to the inputs of any Optimized Global Routing Pool Provides Global GLB on the device. Interconnectivity Lead-Free Package Options Copyright 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2006 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556 Select devices have been discontinued. See Ordering Information section for product status. Specifications ispLSI 2096/A Functional Block Diagram Figure 1. ispLSI 2096/A Functional Block Diagram Input Bus Input Bus Output Routing Pool (ORP) Output Routing Pool (ORP) Megablock Generic Logic C7 C6 C5 C4 C3 C2 C1 C0 Blocks (GLBs) I/O 0 I/O 63 I/O 1 A0 B7 I/O 62 I/O 2 I/O 61 I/O 3 I/O 60 Global I/O 4 I/O 59 I/O 5 I/O 58 A1 Routing B6 I/O 6 I/O 57 I/O 7 I/O 56 Pool I/O 8 I/O 55 (GRP) I/O 9 I/O 54 A2 B5 I/O 10 I/O 53 I/O 11 I/O 52 I/O 12 I/O 51 I/O 13 I/O 50 I/O 14 I/O 49 A3 B4 I/O 15 I/O 48 SDI/IN 0 A4 A5 A6 A7 B0 B1 B2 B3 MODE/IN 1 Output Routing Pool (ORP) Output Routing Pool (ORP) SDO RESET Input Bus Input Bus ispEN 0917 The devices also have 96 I/O cells, each of which is The GRP has as its inputs, the outputs from all of the directly connected to an I/O pin. Each I/O cell can be GLBs and all of the inputs from the bi-directional I/O cells. individually programmed to be a combinatorial input, All of these signals are made available to the inputs of the output or bi-directional I/O pin with 3-state control. The GLBs. Delays through the GRP have been equalized to signal levels are TTL compatible voltages and the output minimize timing skew. drivers can source 4 mA or sink 8 mA. Each output can Clocks in the ispLSI 2096 and 2096A devices are se- be programmed independently for fast or slow output lected using the dedicated clock pins. Three dedicated slew rate to minimize overall output switching noise. clock pins (Y0, Y1, Y2) or an asynchronous clock can be Eight GLBs, 32 I/O cells, two dedicated inputs and two selected on a GLB basis. The asynchronous or Product ORPs are connected together to make a Megablock Term clock can be generated in any GLB for its own clock. (Figure 1). The outputs of the eight GLBs are connected to a set of 32 universal I/O cells by the two ORPs. Each ispLSI 2096 and 2096A device contains three Megablocks. 2 USE ispLSI 2096E FOR NEW DESIGNS GOE 0 Input Bus GOE 1 Output Routing Pool (ORP) I/O 16 I/O 17 I/O 18 I/O 19 I/O 95 I/O 20 I/O 94 I/O 21 I/O 93 I/O 22 I/O 92 I/O 23 I/O 91 I/O 24 I/O 90 I/O 25 I/O 89 I/O 26 I/O 88 I/O 27 I/O 87 I/O 28 I/O 86 I/O 29 I/O 85 I/O 30 I/O 84 I/O 31 I/O 83 I/O 82 I/O 81 I/O 80 IN 2 SCLK/IN 3 I/O 32 I/O 33 I/O 34 I/O 35 I/O 79 I/O 78 I/O 36 I/O 37 I/O 77 I/O 38 I/O 76 I/O 39 I/O 75 I/O 40 I/O 74 I/O 41 I/O 73 I/O 42 I/O 72 I/O 43 I/O 71 I/O 44 I/O 70 I/O 45 I/O 69 I/O 46 I/O 68 I/O 47 I/O 67 I/O 66 I/O 65 I/O 64 IN 5 CLK 0 Y0 IN 4 CLK 1 Y1 CLK 2 Y2 Output Routing Pool (ORP) Input Bus