LFE2M20SE-5F256C Lattice

LatticeECP2/M Family Handbook HB1003 Version 05.3, February 2012 LatticeECP2/M Family Handbook Table of Contents February 2012 Section I. LatticeECP2/M Family Data Sheet Introduction Features ............................................................................................................................................................. 1-1 Introduction ........................................................................................................................................................ 1-2 Architecture Architecture Overview ........................................................................................................................................ 2-1 PFU Blocks ........................................................................................................................................................ 2-3 Slice .......................................................................................................................................................... 2-3 Modes of Operation................................................................................................................................... 2-5 Routing............................................................................................................................................................... 2-6 sysCLOCK Phase Locked Loops (GPLL/SPLL) ................................................................................................ 2-6 General Purpose PLL (GPLL)................................................................................................................... 2-6 Standard PLL (SPLL)................................................................................................................................ 2-7 Delay Locked Loops (DLL)................................................................................................................................. 2-8 DLLDELA Delay Block .............................................................................................................................. 2-9 PLL/DLL Cascading .................................................................................................................................. 2-9 GPLL/SPLL/GDLL PIO Input Pin Connections (LatticeECP2M Family Only) .................................................. 2-10 Clock Dividers .................................................................................................................................................. 2-10 Clock Distribution Network............................................................................................................................... 2-11 Primary Clock Sources............................................................................................................................ 2-11 Secondary Clock/Control Sources .......................................................................................................... 2-13 Edge Clock Sources................................................................................................................................ 2-14 Primary Clock Routing ............................................................................................................................ 2-15 Dynamic Clock Select (DCS) .................................................................................................................. 2-15 Secondary Clock/Control Routing........................................................................................................... 2-15 Slice Clock Selection............................................................................................................................... 2-17 Edge Clock Routing ................................................................................................................................ 2-18 sysMEM Memory ............................................................................................................................................. 2-19 sysMEM Memory Block........................................................................................................................... 2-19 Bus Size Matching .................................................................................................................................. 2-19 RAM Initialization and ROM Operation ................................................................................................... 2-19 Memory Cascading ................................................................................................................................. 2-19 Single, Dual and Pseudo-Dual Port Modes............................................................................................. 2-19 Memory Core Reset................................................................................................................................ 2-20 EBR Asynchronous Reset....................................................................................................................... 2-20 sysDSP Block ............................................................................................................................................... 2-21 sysDSP Block Approach Compared to General DSP ............................................................................. 2-21 sysDSP Block Capabilities...................................................................................................................... 2-21 MULT sysDSP Element .......................................................................................................................... 2-23 MAC sysDSP Element ............................................................................................................................ 2-24 MULTADDSUB sysDSP Element ........................................................................................................... 2-25 MULTADDSUBSUM sysDSP Element ................................................................................................... 2-26 Clock, Clock Enable and Reset Resources ............................................................................................ 2-26 Signed and Unsigned with Different Widths............................................................................................ 2-27 OVERFLOW Flag from MAC .................................................................................................................. 2-27 IPexpress............................................................................................................................................. 2-28 Optimized DSP Functions ................................................................................................................................ 2-28 Resources Available in the LatticeECP2/M Family.................................................................................2-28 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1