LatticeSC/M Family Data Sheet DS1004 Version 02.4, December 2011LatticeSC/M Family Data Sheet Introduction January 2010 Data Sheet DS1004 1 to 7.8 Mbits memory Features True Dual Port/Pseudo Dual Port/Single High Performance FPGA Fabric Port 15K to 115K four input Look-up Tables (LUT4s) Dedicated FIFO logic for all block RAM 139 to 942 I/Os 500MHz performance 700MHz global clock 1GHz edge clocks Additional 240K to 1.8Mbits distributed RAM 4 to 32 High Speed SERDES and flexiPCS sysCLOCK Network (per Device) Eight analog PLLs per device Performance ranging from 600Mbps to 3.8Gbps Frequency range from 15MHz to 1GHz Excellent Rx jitter tolerance (0.8UI at Spread spectrum support 3.125Gbps) 12 DLLs per device with direct control of I/O Low Tx jitter (0.25UI typical at 3.125Gbps) delay Built-in Pre-emphasis and equalization Frequency range from 100MHz to 700MHz Low power (typically 105mW per channel) Extensive clocking network Embedded Physical Coding Sublayer (PCS) 700MHz primary and 325 MHz secondary provides pre-engineered implementation for the clocks following standards: 1GHz I/O-connected edge clocks GbE, XAUI, PCI Express, SONET, Serial Rapi- Precision Clock Divider dIO, 1G Fibre Channel, 2G Fibre Channel Phase matched x2 and x4 division of incom- 2Gbps High Performance PURESPEED I/O ing clocks Supports the following performance bandwidths Dynamic Clock Select (DCS) Differential I/O up to 2Gbps DDR Glitch free clock MUX (1GHz Clock) Masked Array for Cost Optimization Single-ended memory interfaces up to (MACO) Blocks 800Mbps On-chip structured ASIC Blocks provide pre- 144 Tap programmable Input Delay (INDEL) engineered IP for low power, low cost system block on every I/O dynamically aligns data to level integration clock for robust performance Dynamic bit Adaptive Input Logic (AIL) mon- High Performance System Bus itoring and control circuitry per pin that auto- Ties FPGA elements together with a standard matically ensures proper set-up and hold bus framework Dynamic bus: uses control bus from DLL Connects to peripheral user interfaces for Static per bit run-time dynamic configuration Electrical standards supported: System Level Support LVCMOS 3.3/2.5/1.8/1.5/1.2, LVTTL IEEE standard 1149.1 Boundary Scan, plus SSTL 3/2/18 I, II HSTL 18/15 I, II ispTRACY internal logic analyzer PCI, PCI-X IEEE Standard 1532 in-system configuration LVDS, Mini-LVDS, Bus-LVDS, MLVDS, 1.2V and 1.0V operation LVPECL, RSDS Onboard oscillator for initialization and general Programmable On Die Termination (ODT) use Includes Thevenin Equivalent and low Embedded PowerPC microprocessor interface power V termination options TT Low cost wire-bond and high pin count flip-chip packaging Memory Intensive FPGA Low cost SPI Flash RAM configuration sysMEM embedded Block RAM 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1004 Introduction 01.7