LFSCM3GA40EP1-5FFA1020C

LatticeSC/M Family flexiPCS Data Sheet DS1005 Version 02.0, June 2011 Table of Contents LatticeSC/M Family flexiPCS Data Sheet June 2011 Introduction to flexiPCS ..................................................................................................................... 1-1 flexiPCS Features........................................................................................................................................... 1-1 flexiPCS Introduction.......................................................................................................................................... 1-2 Architecture Overview ........................................................................................................................................ 1-2 flexiPCS Quad........................................................................................................................................... 1-2 flexiPCS Channel...................................................................................................................................... 1-3 Per Channel PCS/FPGA Interface Ports................................................................................................... 1-4 Using this Data Sheet ............................................................................................................................... 1-7 SERDES Functionality/Electrical & Timing ......................................................................................2-1 Introduction ........................................................................................................................................................ 2-1 LatticeSC flexiPCS Quad Module ............................................................................................................. 2-1 Quad and Channel Option Control..................................................................................................................... 2-1 Register Map Addressing.......................................................................................................................... 2-1 Auto-Configuration .................................................................................................................................... 2-3 SERDES Functionality ....................................................................................................................................... 2-4 SERDES Port Description.................................................................................................................................. 2-6 SERDES Functionality Detailed Description ...................................................................................................... 2-8 SERDES Powerup .................................................................................................................................... 2-8 Clocks & Resets........................................................................................................................................ 2-9 Rate Mode Registers .............................................................................................................................. 2-12 Locked Reference and Transmit Clocks ................................................................................................. 2-17 Transmit Clocks ...................................................................................................................................... 2-18 Receive Clocks ....................................................................................................................................... 2-18 Transmit Data.......................................................................................................................................... 2-22 Transmit Data Skew................................................................................................................................ 2-23 Receive Data........................................................................................................................................... 2-23 Low Speed SERDES Receiver Operation ....................................................................................................... 2-26 Status Interrupt Registers ................................................................................................................................ 2-27 Receive CDR Loss of Lock Interrupt Usage .................................................................................................... 2-27 flexiPCS Reset Sequences .............................................................................................................................. 2-28 flexiPCS Power Down Control Signals............................................................................................................. 2-29 SERDES Electrical & Timing Characteristics................................................................................................... 2-31 SERDES Performance............................................................................................................................ 2-31 SERDES High Speed Data Transmitter.................................................................................................. 2-31 SERDES High Speed Data Receiver...................................................................................................... 2-33 Interfacing to Reference Clock CML Buffers.................................................................................................... 2-36 SERDES Power ............................................................................................................................................... 2-37 SERDES Power Supply Sequencing Requirements............................................................................... 2-38 SERDES Power Supply Requirements............................................................................................................ 2-38 SERDES Power Supply Package Requirements............................................................................................. 2-38 Power-Down/Power-Up Specification .............................................................................................................. 2-38 8-bit and 10-bit SERDES Only Modes ............................................................................................... 3-1 Introduction ........................................................................................................................................................ 3-1 LatticeSC flexiPCS Quad Module ............................................................................................................. 3-1 Quad and Channel Option Control..................................................................................................................... 3-1 Register Map Addressing.......................................................................................................................... 3-2 Auto-Configuration .................................................................................................................................... 3-3 8-bit SERDES Only Register Settings....................................................................................................... 3-4 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com i