Platform Manager 2
In-System Programmable
Hardware Management Controller
September 2019 Data Sheet FPGA-DS-02036
Features
Ten Rail Voltage Monitoring and FPGA Resources
1280 LUT, 98 I/O Version (LPTM21)
Measurement
UV/OV Fault Detection Accuracy 0.2% Typ. 1280 LUT, 33 I/O Version (LPTM21L)
Fault Detection Speed < 100 s
RAM and Flash Memories
High Voltage, Single Ended and Differential Scalable Hardware Management
Architecture
Sensing
Glueless interface to Hardware Management
Two Channel Wide-Range Current
Expander (L-ASC10)
Monitoring and Measurement
Migrate between LPTM21 and larger density
High-side current measurement up to 12 V
MachXO2, MachXO3, and ECP5 devices
Programmable OC/UC Fault Detect
to extend logic and I/O resources
Detects Current faults in <1 s
System Level Support
Three Temperature Monitoring and
Operating voltage from 2.8 V to 3.46 V
Measurement Channels
Programmable OT/UT Faults Threshold Industrial and commercial temperature ranges
Two channels of Temperature Monitoring using
237-ball ftBGA (LPTM21)
external diodes
100-ball caBGA (LPTM21L)
On-Chip Temperature Monitor
RoHS compliant and halogen-free
4 High-Side MOSFET Drivers
Applications
Programmable Charge Pump
Telecommunication and Networking
Four Precision Trim and Margin Channels Industrial, Test and Measurement
Closed Loop Operation
Medical Systems
Voltage Scaling and VID Support
Servers and Storage Systems
Ten General Purpose Input/Output High Reliability Systems
5 V tolerant I/O
Non-Volatile Fault Logging
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Programmed through JTAG or I C
Background Update with Dual-Boot Backup
Application Diagram
Hardware Management Application Block Diagram
10 Rails
Hot Swap Optional POL
Rs 0.6 V to 5.7 V
Input Rail
Vin Vout
Up to 12 V
EN Trim/FB
Trim/Margin [1:4]
HVOUT [1:4] GPIO Voltage
Current
[1..10] Monitor [1:10]
Monitor
[1:2]
On-Die
NV Fault
Board Temp
Temp
Log
Transistor
ASC Section
Voltage, Current, Temp (VIT)
Temp [1:2]
Measurement and Programming
On-Die Temp
Voltage, Current, Temp
Diode
ADC
(VIT) High Speed
ASIC Fault Detect/Alarms
2
I C
CPU
Resets
Fan(s) Platform Manager 2 FPGA Section
VID
JTAG Programming
2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
www.latticesemi.com 1 FPGA-DS-02036_2.2Platform Manager 2
In-System Programmable
Hardware Management Controller
Description
The Lattice Platform Manager 2 device is a fast-reacting, programmable logic based hardware management con-
troller. Platform Manager 2 is an integrated solution combining analog sense and control elements with scalable
programmable logic resources. This unique approach allows Platform Manager 2 to integrate Power Management
(Power Sequencing, Voltage Monitoring, Trimming and Margining), Thermal Management (Temperature Monitor-
ing, Fan Control, Power Control), and Control Plane functions (System Configuration, I/O Expansion, etc.) as a sin-
gle device.
Architecturally, the Platform Manager 2 device can be divided into two sections Analog Sense and Control and
FPGA. The Analog Sense and Control (ASC) section provides three types of analog sense channels: voltage (nine
standard channels and one high voltage channel), current (one standard voltage and one high voltage) and tem-
perature (two external and one internal).
Each of the analog sense channels is monitored through two independently programmable comparators to support
both high/low and in-bounds/out-of-bounds (window-compare) monitor functions. In addition, each of the current
sense channels provides a fast fault detect (one s response time) for detecting short circuit events. The tempera-
ture sense channels can be configured to work with different external transistor or diode configurations.
The Analog Sense and Control section also provides ten general purpose 5 V tolerant open-drain digital input/out-
put pins that can be used for controlling DC-DC converters, low-drop-out regulators (LDOs) and opto-couplers, as
well as for general purpose logic interface functions. In addition, four high-voltage charge pumped outputs
(HVOUT1-HVOUT4) may be configured as high-voltage MOSFET drivers to control high-side MOSFET switches.
These HVOUT outputs can also be programmed as static output signals or as switched outputs (to support exter-
nal charge pump implementation) operating at a dedicated duty cycle and frequency.
The ASC section incorporates four TRIM outputs for controlling the output voltages of DC-DC converters. Each
power supply output voltage can be maintained typically within 0.5% tolerance across various load conditions using
the Digital Closed Loop Control mode of the trimming block.
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The internal 10-bit A/D converter can be used to measure the voltage and current through the I C bus. The ADC is
also used in the digital closed loop control mode of the trimming block.
The ASC section also provides the capability of logging up to 16 status records into its nonvolatile EEPROM mem-
ory. Each record includes voltage, current and temperature monitor signals along with digital input and output lev-
els.
The ASC section includes an output control block (OCB) which allows certain inputs and control signals a direct
connection to the digital outputs or HVOUTs, bypassing the ASC-I/F for a faster response. The OCB is used to con-
nect the fast current fault detect signal to an FPGA input directly. It also supports functions such as Hot Swap with
a programmable hysteretic controller.
The FPGA section contains non-volatile low cost programmable logic of 1280 Look-Up Tables (LUTs). In addition to
the LUT-based logic, the FPGA section features Embedded Block RAM (EBR), Distributed RAM, User Flash Mem-
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ory (UFM), flexible I/Os, and hardened versions of commonly used functions such as SPI controller, I C controller
and Timer/counter. The FPGA I/Os offer enhanced features such as drive strength control, slew rate control, bus-
keeper latches, internal pull-up or pull-down resistors, and open-drain outputs. These features are controllable on a
per-pin basis.
The power management, thermal management and control plane logic functions are implemented in the FPGA
section of Platform Manager 2. The FPGA receives the analog comparator values and inputs from the ASC section
and sends output commands to the ASC section through the dedicated ASC-interface (ASC-I/F) high-speed, reli-
able serial channel. The FPGA hardware management functions are implemented using the Platform Designer tool
inside Lattice Diamond software. The Platform Designer tool includes an easy to use sequence and monitor logic
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