PCI-EXP1-PM-U3 Lattice

PCI Express 2.0 x1, x4 Endpoint IP Core Users Guide October 2014 IPUG75_2.2Table of Contents Chapter 1. Introduction .......................................................................................................................... 6 Quick Facts ........................................................................................................................................................... 7 Features ................................................................................................................................................................ 7 PHY Layer.................................................................................................................................................... 7 Data Link Layer............................................................................................................................................ 8 Transaction Layer ........................................................................................................................................ 8 Configuration Space Support....................................................................................................................... 8 Top Level IP Support ................................................................................................................................... 8 Chapter 2. Functional Description ...................................................................................................... 10 Overview ............................................................................................................................................................. 10 Interface Description ........................................................................................................................................... 23 Transmit TLP Interface............................................................................................................................... 23 Receive TLP Interface................................................................................................................................ 31 Using the Transmit and Receive Interfaces ........................................................................................................ 33 As a Completer .......................................................................................................................................... 34 As a Requestor .......................................................................................................................................... 35 Unsupported Request Generation ...................................................................................................................... 35 Configuration Space............................................................................................................................................ 36 Base Configuration Type0 Registers ......................................................................................................... 36 Power Management Capability Structure................................................................................................... 36 MSI Capability Structure ............................................................................................................................ 36 How to Enable/Disable MSI ....................................................................................................................... 36 How to issue MSI ....................................................................................................................................... 37 PCI Express Capability Structure............................................................................................................... 37 Device Serial Number Capability Structure................................................................................................ 37 Advanced Error Reporting Capability Structure ......................................................................................... 37 Handling of Configuration Requests .......................................................................................................... 37 Wishbone Interface ............................................................................................................................................. 38 Wishbone Byte/Bit Ordering....................................................................................................................... 38 Error Handling..................................................................................................................................................... 41 Chapter 3. Parameter Settings ............................................................................................................ 46 General Tab ........................................................................................................................................................ 48 PCI Express Link Configuration ................................................................................................................. 48 Use Hard LTSSM MACO Block (LatticeSCM Only)................................................................................... 49 Include System Bus Interface for PCS Access (LatticeSCM Only)............................................................ 49 Include Wishbone Interface........................................................................................................................ 49 Endpoint Type............................................................................................................................................ 49 PCS Pipe Options Tab........................................................................................................................................ 50 Config......................................................................................................................................................... 50 Quad Location............................................................................................................................................ 50 Physical Layer Tab.............................................................................................................................................. 50 Include Master Loopback Data Path.......................................................................................................... 51 Data Link Layer Tab............................................................................................................................................ 51 Update Flow Control Generation Control................................................................................................... 51 Number of P TLPs Between UpdateFC ..................................................................................................... 51 Number of PD TLPs Between UpdateFC................................................................................................... 51 Number of NP TLPs Between UpdateFC................................................................................................... 51 Number of NPD TLPs Between UpdateFC................................................................................................ 51 Worst Case Number of 125MHz Clock Cycles Between UpdateFC.......................................................... 52 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. IPUG75_02.2, October 2014 2 PCI Express 2.0 x1, x4 IP Core Users Guide