MX25L8006E MX25L8006E 3V, 8M-BIT x 1/x 2 CMOS SERIAL FLASH MEMORY Key Features Hold Feature Low Power Consumption Auto Erase and Auto Program Algorithms Additional 512 bit secured OTP for unique identifier P/N: PM1613 Rev. 1.6, August 28, 2017 1MX25L8006E Contents FEATURES ..................................................................................................................................................................5 GENERAL DESCRIPTION .........................................................................................................................................6 PIN CONFIGURATIONS .............................................................................................................................................7 PIN DESCRIPTION ......................................................................................................................................................7 BLOCK DIAGRAM .......................................................................................................................................................8 MEMORY ORGANIZATION .........................................................................................................................................9 Table 1. Memory Organization ............................................................................................................................. 9 DEVICE OPERATION ................................................................................................................................................10 Figure 1. Serial Modes Supported ...................................................................................................................... 10 DATA PROTECTION .................................................................................................................................................. 11 Table 2. Protected Area Sizes ............................................................................................................................ 12 Table 3. 512 bit Secured OTP Definition ............................................................................................................ 13 HOLD FEATURE ........................................................................................................................................................14 Figure 2. Hold Condition Operation ................................................................................................................... 14 COMMAND DESCRIPTION .......................................................................................................................................15 Table 4. COMMAND DEFINITION ..................................................................................................................... 15 (1) Write Enable (WREN) ................................................................................................................................... 16 (2) Write Disable (WRDI) .................................................................................................................................... 16 (3) Read Status Register (RDSR) ...................................................................................................................... 16 Table 5. Status Register .................................................................................................................................... 17 (4) Write Status Register (WRSR) ...................................................................................................................... 17 Table 6. Protection Modes .................................................................................................................................. 18 (5) Read Data Bytes (READ) ............................................................................................................................. 19 (6) Read Data Bytes at Higher Speed (FAST READ) ....................................................................................... 19 (7) Dual Output Mode (DREAD) ......................................................................................................................... 19 (8) Sector Erase (SE) ......................................................................................................................................... 19 (9) Block Erase (BE) ........................................................................................................................................... 20 (10) Chip Erase (CE) .......................................................................................................................................... 20 (11) Page Program (PP) ..................................................................................................................................... 20 (12) Deep Power-down (DP) .............................................................................................................................. 21 (13) Release from Deep Power-down (RDP), Read Electronic Signature (RES) ............................................. 21 (14) Read Identification (RDID) .......................................................................................................................... 22 (15) Read Electronic Manufacturer ID & Device ID (REMS) .............................................................................. 22 Table 7. ID DEFINITIONS ................................................................................................................................. 22 (16) Enter Secured OTP (ENSO) ....................................................................................................................... 22 (17) Exit Secured OTP (EXSO) .......................................................................................................................... 22 (18) Read Security Register (RDSCUR) ............................................................................................................ 23 Table 8. SECURITY REGISTER DEFINITION ................................................................................................... 23 (19) Write Security Register (WRSCUR) ............................................................................................................ 23 P/N: PM1613 Rev. 1.6, August 28, 2017 2