XRT8001 WAN Clock for T1 and E1 Systems October 2001-1 GENERAL DESCRIPTION Generates Output Clock Frequencies Ranging From 8kHz up to 16.384MHz The XRT8001 WAN Clock is a dual-phase-locked loop Serial Port Control for Optimal Performance chip that generates two very low jitter output clock Sync Output: 8kHz or 64kHz signals that can be used for synchronization clocks in wide area networking systems. The XRT8001 has pre- Low Jitter programmed multipliers and dividers that are selected Cascadable (Master / Slave Modes) via the serial port. It generates two integer multiples of No External Components Needed 8kHz, 56kHz, and 64kHz while locked onto an incom- Pin Compatible with the XRT8000 ing reference of 1.54MHz (T1), 2.048MHz (E1), 8kHz, 56kHz, or 64kHz Low Power (3.3V or 5V): 40 - 100mW - 40C to +85C Temperature Range The XRT8001 WAN Clock can be configured to oper- 18-Lead PDIP or SOIC Packages ate in one of six modes: 1. The Forward/Master Mode APPLICATIONS 2. The Reverse/Master Mode T1/E1 Access Equipment (DSU/CSU) 3. The Fractional T1/E1 Reverse/Master Mode Frame Relay Access Devices (FRAD) 4. The E1 to T1 - Forward/Maste Mode Basic Rate and Primary Rate ISDN Equipment 5. The High Speed - Revers Mode ISDN Routers 6. The Slave Mode Terminals Remote Access Servers FEATURES T1/E1 Concentrators Dual Phased Locked Loops with T1/E1 Multiplexers Pre-Programmed Multipliers and Dividers T1/E1 Clock Rate Converters Pre-Programmed with Popular Frequency Internal Timing Generators Conversions for Communications Systems System Synchronizers 3.3V or 5V V CC Reference Clock FIN CLK1 Clock Output 1 6 3 8kHz to 16.384 MHz XRT8001 Sync Out CLK2 Clock Output 2 SYNC 13 2 8kHz or 64kHz Master/Slave MSB PLL Lock Detect LOCKDET 11 8 CS SDO SDI SCLK mmC/mmP Serial I/O Figure 1. System Diagram ORDERING INFORMATION Part Number Package Operating Temperature Range XRT8001IP 18-Lead 300 Mil PDIP -40 C to +85 C XRT8001ID 18-Lead 300 Mil JEDEC SOIC -40C to +85C Rev. 1.01 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.comXRT8001 12 10 7 15 Analog Vcc Digital Vcc Digital Vcc Digital Vcc Analog 13 Post Driver CLK2 Phase Locked Divider Q Loop Feedback Divider Q2 M PLL2 M2 11 LDETDIS1 Lock LOCKDET Detector LDETDIS2 2 SYNC Analog 6 Post Driver CLK1 3 Phase Locked Input Divider FIN Q Loop Divider P Vcc Feedback Divider M PLL1 R R 100K 100K M2 Q2 18 SCLK 17 Mode and Frequency Select Control CS Serial 16 Interface SDI 1 SDO 8 MSB AGND DGND DGND DGND 4 5 14 9 Figure 2. XRT8001 Block Diagram Rev. 1.01 2