XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR AUGUST 2004 REV. 1.1.2 Per-channel transmit power shutdown GENERAL DESCRIPTION Tri-state transmit output capability The XRT82L24A is a fully integrated Quad (four chan- nels) short-haul line interface unit for E1(2.048Mbps) On chip per-channel driver failure monitoring circuit 75 or 120 applications. Each channel consists of a On chip HDB3/B8ZS/AMI encoder/decoder func- receiver with equalizer for reliable data and clock re- tions covery, and a transmitter which accepts either single Supports Gapped Clock for Multiplexer Mapper or dual-rail digital inputs for signal transmission to the Applications line using a low output impedance line driver. The de- Transmit return loss meets or exceeds ETSI 300 vice also includes a crystal-less jitter attenuator 166 standard which, depending on system requirements, can be selected in the receive or transmit path through the Meets or exceeds specifications in ITU G.703, Host or Hardware Mode control. G.775, G.736 and G.823 ETSI 300-166 XRT82L24A is a low power CMOS device operating Meets or exceeds G.783 and G.823 Jitter Specifi- on a single 3.3V supply with 5V tolerant digital inputs. cations 3.3V or 5.0V Logic level inputs FEATURES Fully integrated quad, short-haul PCM transceivers Single +3.3V Supply Operation for E1 applications. New Patent 6,313,671B1 Low Power IC I/O Buffer On Chip Receive Equalizer and Transmit Pulse APPLICATIONS Shaper for CEPT 75 and 120 line terminations Digital cross connects (DSX-1) On chip clock recovery circuit Channel Banks Transformer or capacitor coupled receiver inputs High speed data transmission line cards Crystal-less jitter attenuator can be selected in the E1 Multiplexer transmit or receive path Public switching systems and PBX interfaces High receiver interference immunity FIGURE 1. BLOCK DIAGRAM OF THE XRT82L24A E1 LIU (HOST MODE) Driver TVDD n Monitor TxClk n/RZData n HDB3 Tx/Rx Jitter Tx Timing Tx Pulse Line TTIP n TxPOS n/TDATA n MUX Encoder Attenuator Control Shaper Driver TRing n TxNEG n Remote Local TGND n LoopBack Enable/ Analog LoopBack Disable Digital Clock LoopBack Generator MClk RxClk n RTIP n Peak HDB3 Tx/Rx Jitter Timing & Data Rx RxPOS n/RDATA n MUX Detector Decoder Attenuator Recovery Equalizer & Slicer RxNEG n/LCV n RRing n LOS Detect RxLOS n Channel 0 Channel 1 Channel 2 Channel 3 INT ADD 0:3 RDY DTACK D 0:7 PClk/Codes WR R/W/TxOFF 0 P Controller & Hardware Interface PTS1/ClkE ALE AS/TxOFF 2 PTS2/SR DR CS/TxOFF 3 Reset RD DS/TxOFF 1 ICT HW/HOST Test Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.2 FIGURE 2. BLOCK DIAGRAM OF THE XRT82L24A T1/E1/J LIU (HARDWARE MODE) One of four channels Driver TVDD n Monitor TxClk n/RZData HDB3 Tx/Rx Jitter Tx Timing Tx Pulse Line TTIP n TxPOS n/TDATA n MUX Encoder Attenuator Control Shaper Driver TRing n TxNEG n Remote Local TGND n LoopBack Analog Enable/ LoopBack Disable Digital Clock LoopBack Generator MClk RxClk n RTIP n Peak HDB3 Tx/Rx Jitter Timing & Data Rx RxPOS n/RDATA n MUX Detector Decoder Attenuator Recovery Equalizer & Slicer RxNEG n/LCV n RRing n LOS RxLOS n Detect INT ADD 0 RDY DTACK ADD 1 PClk/Codes ADD 2 PTS1/ClkE ADD 3 /RxMute PTS2/SR/DR D 0 /FIFOS Reset D 1 /LOOPEN 0 P Controler & Hardware Interface WR R/W/TxOFF0 D 2 /LOOPEN 1 ALE AS/TxOFF2 D 3 /LOOPEN 2 CS/TxOFF3 D 4 LOOPEN 3 RD DS/TxOFF1 D 5 /LOOPSEL HW/HOST D 6 /RxJA D 7 TxJA ICT Test 2