XRT83SH38 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT SEPTEMBER 2006 REV. 1.0.7 The on-chip clock synthesizer generates T1/E1/J1 GENERAL DESCRIPTION clock rates from a selectable external clock frequency The XRT83SH38 is a fully integrated 8-channel short- and outputs a clock reference of the line rate chosen. haul line interface unit (LIU) that operates from a Additional features include RLOS, a 16-bit LCV single 3.3V power supply. Using internal termination, counter for each channel, AIS, QRSS generation/ the LIU provides one bill of materials to operate in T1, detection, TAOS, DMO, and diagnostic loopback E1, or J1 mode with minimum external components. modes. The LIU features are programmed through a standard microprocessor interface, serial interface or APPLICATIONS controlled through Hardware mode. EXARs LIU has T1 Digital Cross-Connects (DSX-1) patented high impedance circuits that allow the transmitter outputs and receiver inputs to be high ISDN Primary Rate Interface impedance when experiencing a power failure or CSU/DSU E1/T1/J1 Interface when the LIU is powered off. Key design features within the LIU optimize 1:1 or 1+1 redundancy and T1/E1/J1 LAN/WAN Routers non-intrusive monitoring applications to ensure Public switching Systems and PBX Interfaces reliability without using relays. T1/E1/J1 Multiplexer and Channel Banks FIGURE 1. BLOCK DIAGRAM OF THE XRT83SH38 T1/E1/J1 LIU (HOST MODE) MCLKE1 MCLKOUT MASTER CLOCK SYNTHESIZER MCLKT1 DRIVE 1 of 8 channels, CHANNEL n TAOS DMO n MONITOR TPOS n/TDATA n TTIP n QRSS HDB3/ TX FILTER TX/RX JITTER TIMING LINE TNEG n/CODES n PATTERN B8ZS & PULSE ATTENUATOR CONTROL DRIVER GENERATOR ENCODER SHAPER TCLK n TRING n TXON n Remote Digital Analog Loopback Loopback Loopback QRSS DETECTOR RCLK n HDB3/ TIMING & PEAK RTIP n TX/RX JITTER B8ZS DATA DETECTOR RNEG n/LCV n ATTENUATOR DECODER RECOVERY & SLICER RPOS n/RDATA n RRING n LOS AIS DETECTOR DETECTOR RLOS n TEST ICT HW/HOST PTS1 WR R/W PTS2 RD DS D 7:0 ALE-AS MICROPROCESSOR/SERIAL INTERFACE CONTROLLER CS PCLK/SCLK RDY DTACK/SDO A 7:0 /SDI INT RESET SER PAR Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com XRT83SH38 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.7 FIGURE 2. BLOCK DIAGRAM OF THE XRT83SH38 T1/E1/J1 LIU (HARDWARE MODE) MCLKE1 MCLKOUT MASTER CLOCK SYNTHESIZER MCLKT1 TAOS n CLKSEL 2:0 DRIVE 1 of 8 channels, CHANNEL n TAOS MONITOR DMO n TPOS n/TDATA n QRSS HDB3/ TX FILTER TTIP n TX/RX JITTER TIMING LINE PATTERN B8ZS & PULSE TNEG n/CODES n ATTENUATOR CONTROL DRIVER GENERATOR ENCODER SHAPER TCLK n TRING n Remote Digital Analog TXON n Loopback Loopback Loopback QRSS DETECTOR HDB3/ TIMING & PEAK RCLK n TX/RX JITTER RTIP n B8ZS DATA DETECTOR RNEG n/LCV n ATTENUATOR DECODER RECOVERY & SLICER RRING n RPOS n/RDATA n LOOP1 n LOS AIS LOOP0 n DETECTOR DETECTOR RLOS n TEST ICT HW/HOST RESET GAUGE JASEL1 TRATIO SR/DR JASEL0 EQC 4:0 RXTSEL HARWARE CONTROL TXTSEL TCLKE RCLKE TERSELR XRES0 RXMUTE ATAOS RXRES1 2