Graphics Sequential HDL
Mentor Graphics Sequential HDL 1292.1301 is a high-level modeling language for SystemVerilog for digital and mixed-signal designs. It allows users to define registers, counters, FIFOs, queues and other sequential architectures quickly and easily. It also provides powerful language features such as explicit initialization, conditional initialization, user-defined constructs, unique primitives, concurrency and gates. This language also allows for powerful software integration for design verifications and debug tools.