Revision 3 Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology Architecture Supports Ultra-High Utilization Features and Benefits Advanced and Pro (Professional) I/Os Military Temperature Tested and Qualified 700 Mbps DDR, LVDS-Capable I/Os Each Device Tested from 55C to 125C 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation Bank-Selectable I/O Voltagesup to 8 Banks per Chip Firm-Error Immune Single-Ended I/O Standards: LVTTL, LVCMOS 3.3V/ Not Susceptible to Neutron-Induced Configuration Loss 2.5V/1.8V/1.5V/1.2V, 3.3V PCI / 3.3V PCI-X, and Low Power LVCMOS 2.5 V / 5.0 V Input Dramatic Reduction in Dynamic and Static Power Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power Voltage-Referenced I/O Standards: GTL+ 2.5V/3.3V, GTL Low Power Consumption in Flash*Freeze Mode Allows for 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Instantaneous Entry To / Exit From Low-Power Flash*Freeze Class I and II (A3PE3000L only) Mode I/O Registers on Input, Output, and Enable Paths Supports Single-Voltage System Operation Hot-Swappable and Cold-Sparing I/Os Low-Impedance Switches Programmable Output Slew Rate and Drive Strength Programmable Input Delay (A3PE3000L only) High Capacity Schmitt Trigger Option on Single-Ended Inputs (A3PE3000L) 250K to 3M System Gates Weak Pull-Up/-Down Up to 504 kbits of True Dual-Port SRAM IEEE 1149.1 (JTAG) Boundary Scan Test Up to 620 User I/Os Pin-Compatible Packages across the Military ProASIC 3EL Family Reprogrammable Flash Technology Clock Conditioning Circuit (CCC) and PLL 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process Six CCC BlocksOne Block with Integrated PLL in ProASIC3 Live-at-Power-Up (LAPU) Level 0 Support and All Blocks with Integrated PLL in ProASIC3EL Single-Chip Solution Configurable Phase Shift, Multiply/Divide, Delay Capabilities, Retains Programmed Design when Powered Off and External Feedback High Performance Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2V systems) and 350 MHz (1.5 V systems) 350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System Performance SRAMs and FIFOs 3.3 V, 66 MHz, 64-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit Variable-Aspect-Ratio 4,608-Bit RAM Blocks (1, 2, 4, 9, PCI (1.2 V systems) and 18 organizations available) In-System Programming (ISP) and Security True Dual-Port SRAM (except 18) Secure ISP Using On-Chip 128-Bit Advanced Encryption 24 SRAM and FIFO Configurations with Synchronous Standard (AES) Decryption via JTAG (IEEE 1532compliant) Operation: 250 MHz: For 1.2 V Systems FlashLock to Secure FPGA Contents 350 MHz: For 1.5 V Systems High-Performance Routing Hierarchy ARM Processor Support in ProASIC3/EL FPGAs Segmented, Hierarchical Routing and Clock Structure High-Performance, Low-Skew Global Network ARM Cortex-M1 Soft Processor Available with or without Debug Table 1 Military ProASIC3/EL Low-Power Devices ProASIC3/EL Devices A3P250 A3PE600L A3P1000 A3PE3000L 1 ARM Cortex-M1 Devices M1A3P1000 M1A3PE3000L System Gates 250,000 600,000 1M 3M VersaTiles (D-flip-flops) 6,144 13,824 24,576 75,264 RAM kbits (1,024 bits) 36 108 144 504 4,608-Bit Blocks 8 24 32 112 FlashROM Kbits 1 1 1 1 2 Secure (AES) ISP Yes Yes Yes Yes Integrated PLL in CCCs 1 6 1 6 VersaNet Globals 18 18 18 18 I/O Banks 4 8 4 8 Maximum User I/Os 68 270 154 620 Package Pins VQFP VQ100 PQFP PQ208 FBGA FG484 FG144, FG484 FG484, FG896 Notes: 1. Refer to the Cortex-M1 product brief for more information. 2. AES is not available for ARM-enabled ProASIC3/EL devices. A3P250 and A3P1000 support only 1.5 V core operation. Flash*Freeze technology is not available for A3P250 or A3P1000. Pro I/Os are not available on A3P250 or A3P1000. September 2012 I 2011 Microsemi CorporationMilitary ProASIC3/EL Low Power Flash FPGAs 1 I/Os Per Package ProASIC3/EL Low Power Devices A3P250 A3PE600L A3P1000 A3PE3000L ARM Cortex-M1 Devices M1A3P1000 M1A3PE3000L Single- Differential Single- Differential Single- Differential Single- Differential 2 2 2 2 Ended I/O I/O Pairs Ended I/O I/O Pairs Ended I/O I/O Pairs Ended I/O I/O Pairs Package VQ100 68 13 PQ208 154 35 FG144 97 25 FG484 270 135 300 74 341 168 FG896 620 300 Notes: 1. When considering migrating your design to a lower- or higher-density device, refer to the packaging section of the datasheet to ensure you are complying with design and board migration requirements. 2. Each used differential I/O pair reduces the number of single-ended I/Os available by two. 3. indicates RoHS-compliant packages. Refer toMilitary ProASIC3/EL Ordering Informatio on page III for the location of the in the part number. 4. For A3PE3000L devices, the usage of certain I/O standards is limited as follows: SSTL3(I) and (II): up to 40 I/Os per north or south bank LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank 5. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-ended user I/Os available is reduced by one. Military ProASIC3/EL Device Status Military ProASIC3/EL Devices Status M1 Military ProASIC3/EL Devices Status A3P250 Production A3PE600L Production A3P1000 Production M1A3P1000 Production A3PE3000L Production M1A3PE3000L Production II Revision 3