AT24C01D and AT24C02D 2 I C-Compatible (2-wire) Serial EEPROM 1-Kbit (128 x 8) or 2-Kbit (256 x 8) DATASHEET Features Low Voltage Operation 1.7V (V = 1.7V to 3.6V) CC Internally Organized 128 x 8 (1K) or 256 x 8 (2K) 2 I C-Compatible (2-wire) Serial Interface 100kHz Standard Mode, 1.7V to 3.6V 400kHz Fast Mode, 1.7V to 3.6V 1MHz Fast Mode Plus (FM+), 2.5V to 3.6V Schmitt Triggers, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol Write Protect Pin for Full Array Hardware Data Protection Ultra Low Active Current (1mA max) and Standby Current (0.8 A max) 8-byte Page Write Mode Partial Page Writes Allowed Random and Sequential Read Modes Self-timed Write Cycle Within 5ms max High Reliability Endurance: 1,000,000 Write Cycles Data Retention: 100 Years Green Package Options (Lead-free/Halide-free/RoHS Compliant) (1) 8-lead SOIC, 8-lead TSSOP, 8-pad UDFN, 8-lead PDIP , 5-lead SOT23, and 8-ball VFBGA Die Sale Options: Wafer Form and Tape and Reel Description The Atmel AT24C01D/02D provides 1,024/2,048 bits of Serial Electrically Erasable and Programmable Read-Only Memory (EEPROM) organized as 128/256 words of eight bits each. The devices cascadable feature allows up to eight devices to share a common 2-wire bus. These device are optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. Both devices are available in space-saving 8-lead SOIC, (1) 8-lead TSSOP, 8-pad UDFN, 8-lead PDIP , 5-lead SOT23, and 8-ball VFBGA packages. The entire family of packages operates from 1.7V to 3.6V. Note: 1. Contact Atmel Sales for availability of this package. Atmel-8871F-SEEPROM-AT24C01D-02D-Datasheet 0120171. Pin Descriptions and Pinouts Table 1-1. Pin Descriptions Pin Pin Pin Asserted Number Symbol Pin Name and Functional Description State Type Device Address Inputs: The A , A , and A pins are used to select the 0 1 2 hardware device address and correspond to the seventh, sixth, and fifth 2 bit of the I C seven bit slave address. These pins can be directly 1, 2, 3 A , A , A Input 0 1 2 connected to V or GND, allowing up to eight devices on the same bus. CC Refer to Note 1 for behavior of the pin when not connected. Ground: The ground reference for the power supply. GND should be 4 GND Power connected to the system ground. Serial Data: The SDA pin is an open-drain bidirectional input/output pin used to serially transfer data to and from the device. Input/ 5 SDA The SDA pin must be pulled-high using an external pull-up resistor (not to Output exceed 10K in value) and may be wire-ORed with any number of other open-drain or open-collector pins from other devices on the same bus. Serial Clock: The SCL pin is used to provide a clock to the device and to control the flow of data to and from the device. Command and input data present on the SDA pin is always latched in on the rising edge of SCL, 6 SCL Input while output data on the SDA pin is clocked out on the falling edge of SCL. The SCL pin must either be forced high when the serial bus is idle or pulled-high using an external pull-up resistor. Write Protect: Connecting the WP pin to GND will ensure normal write operations.When the WP pin is connected to V , all write operations to CC 7 WP High Input the memory are inhibited. Refer to Note 1 for behavior of the pin when not connected. Device Power Supply: The V pin is used to supply the source voltage CC 8 V to the device. Operations at invalid V voltages may produce spurious Power CC CC results and should not be attempted. Note: 1. If the A , A , A , or WP pins are not driven, they are internally pulled down to GND. In order to operate in a wide 0 1 2 variety of application environments, the pull-down mechanism is intentionally designed to be somewhat strong. Once these pins are biased above the CMOS input buffers trip point (~0.5 x V ), the pull-down mechanism CC disengages. Atmel recommends connecting these pins to a known state whenever possible. 8-pad UDFN 8-lead SOIC 8-lead TSSOP 1 8 A V 0 CC A 1 8 V 0 CC A V 0 1 8 CC A 2 7 A 2 7 WP WP 1 A 2 7 WP 1 1 3 6 A SCL A 3 6 SCL A 3 6 2 2 SCL 2 4 5 GND SDA 4 5 GND SDA GND 4 5 SDA Top View Top View Top View (1) 8-lead PDIP 5-lead SOT23 8-ball VFBGA 1 8 A 1 8 V A V 0 CC 0 CC SCL 1 5 WP A 2 7 WP A 2 7 WP 1 1 GND 2 A 3 6 SCL A 3 6 SCL 2 2 3 4 4 5 SDA V GND SDA CC GND 4 5 SDA Top View Top View Top View Note: Package drawings are not to scale. Note: 1. Refer to Section 4.1, Device Addressing on page 7 for details addressing the SOT23 version of the device. 2 AT24C01D and AT24C02D DATASHEET Atmel-8871F-SEEPROM-AT24C01D-02D-Datasheet 012017