Features
Fast Read Access Time 120 ns
Automatic Page Write Operation
Internal Address and Data Latches for 128 Bytes
Internal Control Timer
Fast Write Cycle Time
Page Write Cycle Time 10 ms Maximum
1 to 128-byte Page Write Operation
Low Power Dissipation
1-megabit
40 mA Active Current
200 A CMOS Standby Current
(128K x 8)
Hardware and Software Data Protection
DATA Polling for End of Write Detection
Paged Parallel
High Reliability CMOS Technology
4 5
or 10 Cycles
Endurance: 10
EEPROM
Data Retention: 10 Years
Single 5V 10% Supply
CMOS and TTL Compatible Inputs and Outputs
AT28C010
JEDEC Approved Byte-wide Pinout
Industrial Temperature Ranges
Green (Pb/Halide-free) Packaging Option Only
1. Description
The AT28C010 is a high-performance electrically-erasable and programmable read-
only memory. Its 1 megabit of memory is organized as 131,072 words by 8 bits. Man-
ufactured with Atmels advanced nonvolatile CMOS technology, the device offers
access times to 120 ns with power dissipation of just 220 mW. When the device is
deselected, the CMOS standby current is less than 200 A.
The AT28C010 is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 128-byte page register to allow
writing of up to 128 bytes simultaneously. During a write cycle, the address and 1 to
128 bytes of data are internally latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the device will automatically write
the latched data using an internal control timer. The end of a write cycle can be
detected by DATA polling of I/O7. Once the end of a write cycle has been detected a
new access for a read or write can begin.
Atmels AT28C010 has additional features to ensure high quality and manufacturabil-
ity. The device utilizes internal error correction for extended endurance and improved
data retention characteristics. An optional software data protection mechanism is
available to guard against inadvertent writes. The device also includes an extra
128 bytes of EEPROM for device identification or tracking.
0353IPEEPR08/09AT28C010
2.2 32-lead PLCC Top View
2. Pin Configurations
Pin Name Function
A0 - A16 Addresses
CE Chip Enable
A7 5 29 A14
A6 6 28 A13
OE Output Enable
A5 7 27 A8
Write Enable
WE
A4 8 26 A9
A3 9 25 A11
I/O0 - I/O7 Data Inputs/Outputs
A2 10 24 OE
NC No Connect
A1 11 23 A10
DC Dont Connect A0 12 22 CE
I/O0 13 21 I/O7
Note: PLCC package pin 1 is Dont Connect.
2.1 32-lead TSOP Top View
A11 1 32 OE
A9 2 31 A10
A8 3 30 CE
A13 4 I/O7
29
A14 5 28 I/O6
NC 6 27 I/O5
WE 7 26 I/O4
VCC 8 25 I/O3
NC 9 24 GND
A16 10 23 I/O2
A15 11 22 I/O1
A12 12 21 I/O0
A7 13 20 A0
A6 14 19 A1
A5 15 18 A2
A4 16 17 A3
2
0353IPEEPR08/09
I/O1 14 4 A12
I/O2 15 3 A15
GND 16 2 A16
I/O3 17 1 DC
I/O4 18 32 VCC
I/O5 19 31 WE
I/O6 20 30 NC