Features Ultra High Performance System Speeds to 100 MHz Array Multipliers > 50 MHz 10nsFlexibleSRAM Internal Tri-state Capability in Each Cell FreeRAM Flexible, Single/Dual Port, Synchronous/Asynchronous 10 ns SRAM 2,048 - 18,432 Bits of Distributed SRAM Independent of Logic Cells 128 - 384 PCI Compliant I/Os 3V/5V Capability 5K - 50K Gates Programmable Output Drive Fast, Flexible Array Access Facilitates Pin Locking Coprocessor Pin-compatible with XC4000, XC5200 FPGAs 8 Global Clocks FPGA with Fast, Low Skew Clock Distribution Programmable Rising/Falling Edge Transitions FreeRAM Distributed Clock Shutdown Capability for Low Power Management Global Reset/Asynchronous Reset Options 4 Additional Dedicated PCI Clocks Cache Logic Dynamic Full/Partial Re-configurability In-System AT40K05 Unlimited Re-programmability via Serial or Parallel Modes Enables Adaptive Designs Enables Fast Vector Multiplier Updates AT40K05LV QuickChange Tools for Fast, Easy Design Changes Pin-compatible Package Options AT40K10 Plastic Leaded Chip Carriers (PLCC) Thin, Plastic Quad Flat Packs (LQFP, TQFP, PQFP) AT40K10LV Ball Grid Arrays (BGAs) Industry-standard Design Tools AT40K20 Seamless Integration (Libraries, Interface, Full Back-annotation) with Concept , Everest, Exemplar ,Mentor , OrCAD ,Synario , Synopsys , AT40K20LV Verilog , Veribest , Viewlogic , Synplicity Timing Driven Placement & Routing Automatic/Interactive Multi-chip Partitioning AT40K40 Fast, Efficient Synthesis Over 75 Automatic Component Generators Create 1000s AT40K40LV of Reusable, Fully Deterministic Logic and RAM Functions Intellectual Property Cores Fir Filters, UARTs, PCI, FFT and Other System Level Functions Easy Migration to Atmel Gate Arrays for High Volume Production Supply Voltage 5V for AT40K, and 3.3V for AT40KLV Rev. 0896CFPGA04/02 1(1) Table 1. AT40K/AT40KLV Family AT40K05 AT40K10 AT40K20 AT40K40 Device AT40K05LV AT40K10LV AT40K20LV AT40K40LV Usable Gates 5K - 10K 10K - 20K 20K - 30K 40K - 50K Rows x Columns 16 x 16 24 x 24 32 x 32 48 x 48 Cells 256 576 1,024 2,304 (1) (1) (1) (1) Registers 256 576 1,024 2,304 RAM Bits 2,048 4,608 8,192 18,432 I/O (Maximum) 128 192 256 384 Note: 1. Packages with FCK will have 8 less registers. Description The AT40K/AT40KLV is a family of fully PCI-compliant, SRAM-based FPGAs with dis- tributed 10 ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global clocks, Cache Logic ability (partially or fully reconfigurable without loss of data), automatic component generators, and range in size from 5,000 to 50,000 usable gates. I/O counts range from 128 to 384 in industry standard packages ranging from 84-pin PLCC to 352-ball Square BGA, and support 5V designs for AT40K and 3.3V designs for AT40KLV. The AT40K/AT40KLV is designed to quickly implement high-performance, large gate count designs through the use of synthesis and schematic-based tools used on a PC or Sun platform. Atmels design tools provide seamless integration with industry standard tools such as Synplicity, ModelSim, Exemplar and Viewlogic. The AT40K/AT40KLV can be used as a coprocessor for high-speed (DSP/processor- based) designs by implementing a variety of computation intensive, arithmetic functions. These include adaptive finite impulse response (FIR) filters, fast Fourier transforms (FFT), convolvers, interpolators and discrete-cosine transforms (DCT) that are required for video compression and decompression, encryption, convolution and other multime- dia applications. Fast, Flexible and The AT40K/AT40KLV FPGA offers a patented distributed 10 ns SRAM capability where the RAM can be used without losing logic resources. Multiple independent, synchronous Efficient SRAM or asynchronous, dual-port or single-port RAM functions (FIFO, scratch pad, etc.) can be created using Atmels macro generator tool. Fast, Efficient Array and The AT40K/AT40KLVs patented 8-sided core cell with direct horizontal, vertical and diagonal cell-to-cell connections implements ultra fast array multipliers without using Vector Multipliers any busing resources. The AT40K/AT40KLVs Cache Logic capability enables a large number of design coefficients and variables to be implemented in a very small amount of silicon, enabling vast improvement in system speed at much lower cost than conven- tional FPGAs. 2 AT40K/AT40KLV Series FPGA 0896CFPGA04/02