AT80C51RD2-SLSUM Microchip

Features 80C52 Compatible Four 8-bit I/O Ports Three 16-bit Timer/Counters 256 Bytes Scratch Pad RAM 8 Interrupt Sources with 4 Priority Levels Dual Data Pointer Variable Length MOVX for Slow RAM/Peripherals High-speed Architecture 80C51 High 10 to 40 MHz in Standard Mode 16K/32K Bytes On-Chip ROM Program Performance AT80C51RD2 ROMless Versions On-Chip 1024 bytes Expanded RAM (XRAM) ROM 8-bit Software Selectable Size (0, 256, 512, 768, 1024 bytes) 256 Bytes Selected at Reset Microcontroller Keyboard Interrupt Interface on Port P1 8-bit Clock Prescaler 64K Program and Data Memory Spaces AT80C51RD2 Improved X2 Mode with Independant Selection for CPU and Each Peripheral Programmable Counter Array 5 Channels with: High-speed Output Compare/Capture Pulse Width Modulator Watchdog Timer Capabilities Asynchronous Port Reset Full Duplex Enhanced UART Dedicated Baud Rate Generator for UART Low EMI (Inhibit ALE) Hardware Watchdog Timer (One-time Enabled with Reset-out) Power Control Modes Idle Mode Power-down Mode Power-off Flag Power Supply: 2.7V to 5.5V Temperature Ranges: Commercial (0 to +70C) and Industrial (-40C to +85C) Packages: PDIL40, PLCC44, VQFP441. Description AT80C51RD2 microcontrollers are high performance versions of the 80C51 8-bit microcontrollers. The microcontrollers retain all features of the Atmel 80C52 with 256 bytes of internal RAM, a 7- source 4-level interrupt controller and three timer/counters. In addition, the microcontrollers have a Programmable Counter Array, an XRAM of 1024 byte, a Hardware Watchdog Timer, a Keyboard Interface, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a speed improvement mechanism (X2 mode). The microcontrollers have 2 software-selectable modes of reduced activity and 8 bit clock pres- caler for further reduction in power consumption. In Idle mode, the CPU is frozen while the peripherals and the interrupt system are still operating. In the Power-down mode, the RAM is saved and all other functions are inoperative. Table 1. Memory Size ROM (Bytes) XRAM (Bytes) TOTAL RAM (Bytes) I/O AT80C51RD2 ROMless 1024 1280 32 2. Block Diagram (2) (2) (1) (1) (1) (1) XTAL1 XTAL2 EUART RAM XRAM + PCA Timer2 256x8 1Kx8 BRG ALE/PROG C51 CORE IB-bus PSEN CPU EA (2) Key Timer 0 INT Parallel I/O Ports & Ext. Bus Watch RD Ctrl Board Timer 1 Dog (2) Port 0Port 1 Port 2 Port 3 WR (2) (2) (2) (2) Notes: 1. Alternate function of Port 1 2. Alternate function of Port 3 2 AT80C51RD2 4113D805101/09 RESET T0 RxD T1 TxD INT0 INT1 VCC P0 Vss P1 P2 P3 ECI PCA T2EX T2