1. Features
Low-voltage and Standard-voltage Operation
2.7(V =2.7Vto5.5V)
CC
1.8(V =1.8Vto5.5V)
CC
User-selectable Internal Organization
2K: 256x8or128x16
4K: 512x8or256x16
Three-wire Serial Interface
Sequential Read Operation
Three-wire
2 MHz Clock Rate (5V)
Self-timed Write Cycle (10 ms Max)
Serial
High Reliability
Endurance: 1 Million Write Cycles
EEPROM
Data Retention: 100 Years
Automotive Devices Available
2K (256 x 8 or 128 x 16)
8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead Ultra Thin mini-MAP
(MLP 2x3), 8-lead Ultra Lead Frame Land Grid Array (ULA), 8-lead TSSOP and 8-ball
4K (512 x 8 or 256 x 16)
dBGA2 Packages
2. Description
AT93C56A
The AT93C56A/66A provides 2048/4096 bits of serial electrically erasable program-
AT93C66A
mable read-only memory (EEPROM) organized as 128/256 words of 16 bits each
(when the ORG pin is connected to VCC) and 256/512 words of 8 bits each (when the
ORG pin is tied to ground). The device is optimized for use in many industrial and
commercial applications where low-power and low-voltage operations are essential.
Not Recommended
The AT93C56A/66A is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-
for New Design.
lead EIAJ SOIC, 8-lead Ultra Thin mini-MAP (MLP 2x3), 8-lead Ultra Lead Frame Land
Replaced by
Grid Array (ULA), 8-lead TSSOP, and 8-ball dBGA2 packages.
AT93C56B or
The AT93C56A/66A is enabled through the Chip Select pin (CS) and accessed via a
three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift
AT93C66B.
Clock (SK). Upon receiving a read instruction at DI, the address is decoded and the
data is clocked out serially on the data output pin DO. The write cycle is completely
self-timed and no separate erase cycle is required before write. The write cycle is only
enabled when the part is in the Erase/Write Enable State. When CS is brought high
following the initiation of a write cycle, the DO pin outputs the Ready/Busy status of
the part.
The AT93C56A/66A is available in 2.7V to 5.5V and 1.8V to 5.5V versions.
3378OSEEPR11/09Table 2-1. Pin Configurations
8-lead SOIC
8-ball dBGA2
Pin Name Function
VCC 8 1 CS CS 1 8 VCC
NC 7 2 SK SK 2 7 NC
CS Chip Select
DI 3 6 ORG
ORG 6 3 DI
5 4 DO 4 5 GND
GND DO
SK Serial Data Clock
Bottom view
DI Serial Data Input
8-lead Ultra Thin mini-MAP (MLP 2x3)
8-lead PDIP
DO Serial Data Output
VCC 8 1 CS CS 1 8 VCC
NC 7 2 SK SK 2 7 NC
GND Ground
ORG 6 3 DI DI 3 6 ORG
DO 4 5 GND
GND 5 4 DO
VCC Power Supply
Bottom view
8-lead Ultra Lead Frame
8-lead TSSOP
ORG Internal Organization
Land Grid Array (ULA)
CS 1 8 VCC
NC No Connect SK 2 7 NC
VCC 8 1 CS
DI 3 6 ORG
NC 7 2 SK
DO 4 5 GND
ORG 6 3 DI
GND 5 4 DO
Bottom view
3. Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under Absolute
Operating Temperature 55 C to +125C
Maximum Ratings may cause permanent dam-
age to the device. This is a stress rating only, and
Storage Temperature 65 C to +150C
functional operation of the device at these or any
Voltage on Any Pin other conditions beyond those indicated in the
with Respect to Ground 1.0V to +7.0V operational sections of this specification is not
implied. Exposure to absolute maximum rating
Maximum Operating Voltage .......................................... 6.25V
conditions for extended periods may affect
device reliability
DC Output Current........................................................ 5.0 mA
2
AT93C56A/66A
3378OSEEPR11/09