ATMEGA64RZAV-10MU

Features High-performance, Low-power Atmel AVR 8-bit Microcontroller Advanced RISC Architecture 131 Powerful Instructions Most Single-clock Cycle Execution 32 8 General Purpose Working Registers Fully Static Operation Up to 20 MIPS Throughput at 20MHz High Endurance Non-volatile Memory segments 64 Kbytes of In-System Self-programmable Flash program memory 2 Kbytes EEPROM 4 Kbytes Internal SRAM 8-bit Atmel (1)(3) Write/Erase cyles: 10,000 Flash/100,000 EEPROM (2)(3) Data retention: 20 years at 85C/100 years at 25C Microcontroller Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program with 64K Bytes True Read-While-Write Operation Programming Lock for Software Security In-System JTAG (IEEE std. 1149.1 Compliant) Interface Boundary-scan Capabilities According to the JTAG Standard Extensive On-chip Debug Support Programmable Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Peripheral Features Flash Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode Real Time Counter with Separate Oscillator ATmega644/V Six PWM Channels 8-channel, 10-bit ADC Differential mode with selectable gain at 1x, 10x or 200x Byte-oriented Two-wire Serial Interface One Programmable Serial USART Master/Slave SPI Serial Interface Programmable Watchdog Timer with Separate On-chip Oscillator On-chip Analog Comparator Interrupt and Wake-up on Pin Change Special Microcontroller Features Power-on Reset and Programmable Brown-out Detection Internal Calibrated RC Oscillator External and Internal Interrupt Sources Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby I/O and Packages 32 Programmable I/O Lines 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF Speed Grades ATmega644V: 0 - 4MHz 1.8V - 5.5V, 0 - 10MHz 2.7V - 5.5V ATmega644: 0 - 10MHz 2.7V - 5.5V, 0 - 20MHz 4.5V - 5.5V Power Consumption at 1MHz, 3V, 25C Active: 240A 1.8V, 1MHz Power-down Mode: 0.1A 1.8V Notes: 1. Worst case temperature. Guaranteed after last write cycle. 2. Failure rate less than 1 ppm. 3. Characterized through accelerated tests. 2593OAVR02/121. Pin Configurations Figure 1-1. Pinout ATmega644 PDIP (PCINT8/XCK0/T0) PB0 PA0 (ADC0/PCINT0) (PCINT9/CLKO/T1) PB1 PA1 (ADC1/PCINT1) (PCINT10/INT2/AIN0) PB2 PA2 (ADC2/PCINT2) (PCINT11/OC0A/AIN1) PB3 PA3 (ADC3/PCINT3) (PCINT12/OC0B/SS) PB4 PA4 (ADC4/PCINT4) (PCINT13/MOSI) PB5 PA5 (ADC5/PCINT5) (PCINT14/MISO) PB6 PA6 (ADC6/PCINT6) (PCINT15/SCK) PB7 PA7 (ADC7/PCINT7) RESET AREF VCC GND GND AVCC XTAL2 PC7 (TOSC2/PCINT23) XTAL1 PC6 (TOSC1/PCINT22) (PCINT24/RXD0) PD0 PC5 (TDI/PCINT21) (PCINT25/TXD0) PD1 PC4 (TDO/PCINT20) (PCINT26/INT0) PD2 PC3 (TMS/PCINT19) (PCINT27/INT1) PD3 PC2 (TCK/PCINT18) (PCINT28/OC1B) PD4 PC1 (SDA/PCINT17) (PCINT29/OC1A) PD5 PC0 (SCL/PCINT16) (PCINT30/OC2B/ICP) PD6 PD7 (OC2A/PCINT31) TQFP/QFN/MLF (PCINT13/MOSI) PB5 PA4 (ADC4/PCINT4) (PCINT14/MISO) PB6 PA5 (ADC5/PCINT5) (PCINT15/SCK) PB7 PA6 (ADC6/PCINT6) RESET PA7 (ADC7/PCINT7) VCC AREF GND GND XTAL2 AVCC XTAL1 PC7 (TOSC2/PCINT23) (PCINT24/RXD0) PD0 PC6 (TOSC1/PCINT22) (PCINT25/TXD0) PD1 PC5 (TDI/PCINT21) (PCINT26/INT0) PD2 PC4 (TDO/PCINT20) Note: The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure good mechanical stability. 2 ATmega644 2593OAVR02/12 PB4 (SS/OC0B/PCINT12) (PCINT27/INT1) PD3 PB3 (AIN1/OC0A/PCINT11) (PCINT28/OC1B) PD4 PB2 (AIN0/INT2/PCINT10) (PCINT29/OC1A) PD5 PB1 (T1/CLKO/PCINT9) (PCINT30/OC2B/ICP) PD6 PB0 (XCK0/T0/PCINT8) (PCINT31/OC2A) PD7 GND VCC VCC GND PA0 (ADC0/PCINT0) (PCINT16/SCL) PC0 PA1 (ADC1/PCINT1) (PCINT17/SDA) PC1 PA2 (ADC2/PCINT2) (PCINT18/TCK) PC2 PA3 (ADC3/PCINT3) (PCINT19/TMS) PC3