KSZ8765CLX Integrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMII/RGMII and MII/ RMII Interfaces Robust PHY Ports Target Applications - Four Integrated IEEE 802.3/802.3u-Compli- Industrial Ethernet Applications that Employ IEEE ant Ethernet Transceivers Port 1 and Port 2 802.3-Compliant MACs. (Ethernet/IP, Profinet, Support 100Base-FX, Port 3 and Port 4 Sup- MODBUS TCP, etc.) port 10/100Base-T/TX VoIP Phone - 802.1az EEE Supported Set-Top/Game Box - On-Chip Termination Resistors and Internal Automotive Biasing for Differential Pairs to Reduce Industrial Control Power IPTV POF - HP Auto MDI/MDI-X Crossover Support Elim- inates the Need to Differentiate Between SOHO Residential Gateway with Full-Wire Speed of Four LAN Ports Straight or Crossover Cables in Applications MAC and GMAC Ports Broadband Gateway/Firewall/VPN - Four Internal Media Access Control (MAC1 to Integrated DSL/Cable Modem MAC4) Units and One Internal Gigabit Media Wireless LAN Access Point + Gateway Access Control (GMAC5) Unit Standalone 10/100 Switch - GMII, RGMII, MII, or RMII Interfaces Support Networked Measurement and Control Systems for the Port 5 GMAC5 with Uplink - 2 KByte Jumbo Packet Support Features - Tail Tagging Mode (One Byte Added Before Management Capabilities FCS) Support on Port 5 to Inform the Proces- - The KSZ8765CLX Includes All the Functions sor in which the Ingress Port Receives the Packet and its Priority of a 10/100BASE-T/TX Switch System Which Combines a Switch Engine, Frame Buffer - Supports Reduced Media Independent Inter- Management, Address Look-Up Table, face (RMII) with 50 MHz Reference Clock Queue Management, MIB Counters, Media Output Access Controllers (MAC), and PHY Trans- - Supports Media Independent Interface (MII) ceivers in Either PHY Mode or MAC Mode on Port 5 - Non-Blocking Store-and-Forward Switch Cable Diagnostic Capabilities for - LinkMD Fabric Assures Fast Packet Delivery by Uti- Determining Cable Opens, Shorts, and lizing a 1024-Entries Forwarding Table Length - Port Mirroring/Monitoring/Sniffing: Ingress Advanced Switch Capabilities and/or Egress Traffic to Any Port - Non-Blocking Store-and-Forward Switch - MIB Counters for Fully-Compliant Statistics Fabric Assures Fast Packet Delivery by Uti- Gathering (36 Counters per Port) lizing 1024 Entry Forwarding Table - Support Hardware for Port-Based Flush and - 64 KB Frame Buffer RAM Freeze Command in MIB Counter. - IEEE 802.1q VLAN Support for up to 128 - Multiple Loopback of Remote, PHY, and MAC Active VLAN Groups (Full-Range 4096 of Modes Support for the Diagnostics VLAN IDs) - Rapid Spanning Tree Support (RSTP) for - IEEE 802.1p/Q Tag Insertion or Removal on Topology Management and Ring/Linear a Per Port Basis (Egress) Recovery - VLAN ID Tag/Untag Options on Per Port Basis - Fully Compliant with IEEE 802.3/802.3u Standards - IEEE 802.3x Full-Duplex with Force-Mode 2016 Microchip Technology Inc. DS00002130A-page 1KSZ8765CLX Option and Half-Duplex Back-Pressure Colli- Power and Power Management sion Flow Control - Full-Chip Software Power-Down (All Register - IEEE 802.1w Rapid Spanning Tree Protocol Values are Not Saved and Strap-In value Will Support Re-Strap after it Releases the Power-Down) - IGMP v1/v2/v3 Snooping for Multicast Packet - Per-Port Software Power-Down Filtering - Energy Detect Power-Down (EDPD), which - QoS/CoS Packets Prioritization Support: Disables the PHY Transceiver When Cables 802.1p, DiffServ-Based and Re-Mapping of are Removed 802.1p Priority Field Per Port Basis on Four - Supports IEEE P802.3az Energy Efficient Priority Levels Ethernet (EEE) to Reduce Power Consump- - IPv4/IPv6 QoS Support tion in Transceivers in LPI State Even Though Cables are Not Removed - IPV6 Multicast Listener Discovery (MLD) Snooping - Dynamic Clock Tree Control to Reduce Clocking in Areas that are Not in Use - Programmable Rate Limiting at the Ingress and Egress Ports on a Per Port Basis - Low Power Consumption without Extra Power Consumption on Transformers - Jitter-Free Per Packet Based Rate Limiting Support - Voltages: Using External LDO Power Sup- plies - Tail Tag Mode (1 byte Added before FCS) Support on Port 5 to Inform the Processor - Analog VDDAT 3.3V or 2.5V which Ingress Port Receives the Packet - VDDIO Support 3.3V, 2.5V, and 1.8V - Broadcast Storm Protection with Percentage - Low 1.2V Voltage for Analog and Digital Core Control (Global and Per Port Basis) Power - 1K Entry Forwarding Table with 64 KB Frame - WoL Support with Configurable Packet Con- Buffer trol - 4 Priority Queues with Dynamic Packet Map- Additional Features ping for IEEE 802.1P, IPV4 TOS (DIFF- - Single 25 MHz +50 ppm Reference Clock SERV), IPv6 Traffic Class, etc. Requirement - Supports WoL Using AMDs Magic Packet - Comprehensive Programmable Two-LED - VLAN and Address Filtering Indicator Support for Link, Activity, Full-/Half- - Supports 802.1x Port-Based Security, Duplex, and 10/100 Speed Authentication and MAC-Based Authentica- Packaging and Environmental tion via Access Control Lists (ACL) - Commercial Temperature Range: 0C to - Provides Port-Based and Rule-Based ACLs +70C to Support Layer 2 MAC SA/DA Address, - Industrial Temperature Range: 40C to Layer 3 IP Address and IP Mask, Layer 4 +85C TCP/UDP Port Number, IP Protocol, TCP - Package Available in an 80-Pin LQFP, Lead- Flag and Compensation for the Port Security Free (RoHS-Compliant) Package Filtering - Supports Human Body Model (HBM) ESD - Ingress and Egress Rate Limit Based on Bit Rating of 5 kV per Second (bps) and Packet-Based Rate - 0.065 m CMOS Technology for Lower Limiting (pps) Power Consumption Configuration Registers Access - High-Speed SPI (4-Wire, up to 50 MHz) Inter- face to Access All Internal Registers - MII Management (MIIM, MDC/MDIO 2-Wire) Interface to Access All PHY Registers per Clause 22.2.4.5 of the IEEE 802.3 Specifica- tion - I/O Pin Strapping Facility to Set Certain Reg- ister Bits from I/O Pins During Reset Time - Control Registers Configurable On-the-Fly 2016 Microchip Technology Inc. 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