KSZ8863RLL

KSZ8863MLL/FLL/RLL Integrated 3-Port 10/100 Managed Switch with PHYs - Non-Blocking Switch Fabric Ensures Fast Features Packet Delivery by Utilizing a 1k MAC Address Advanced Switch Features Lookup Table and a Store-and-Forward Archi- - IEEE 802.1q VLAN Support for Up to 16 Groups tecture (Full Range of VLAN IDs) - Full-Duplex IEEE 802.3x Flow Control (PAUSE) - VLAN ID Tag/Untag Options, Per Port Basis with Force Mode Option - IEEE 802.1p/q Tag Insertion or Removal on a - Half-Duplex Back Pressure Flow Control Per Port Basis (Egress) - HP Auto MDI-X for Reliable Detection of and - Programmable Rate Limiting at the Ingress and Correction for Straight-Through and Crossover Egress on a Per Port Basis Cables with Disable and Enable Option - Broadcast Storm Protection with Percent Con- -LinkMD TDR-Based Cable Diagnostics Permit trol (Global and Per Port Basis) Identification of Faulty Copper Cabling - IEEE 802.1d Rapid Spanning Tree Protocol - MII Interface Supports Both MAC Mode and Support PHY Mode - Tail Tag Mode (1 byte Added before FCS) Sup- - Comprehensive LED Indicator Support for Link, port at Port 3 to Inform the Processor which Activity, Full-/Half-Duplex and 10/100 Speed Ingress Port Receives the Packet and its Prior- - HBM ESD Rating 4 kV ity Switch Monitoring Features - Bypass Feature that Automatically Sustains the - Port Mirroring/Monitoring/Sniffing: Ingress and/ Switch Function between Port 1 and Port 2 or Egress Traffic to Any Port or MII when CPU (Port 3 Interface) Goes to the Sleep - MIB Counters for Fully Compliant Statistics Mode Gathering 34 MIB Counters Per Port - Self-Address Filtering - Loopback Modes for Remote Diagnostic of Fail- - Individual MAC Address for Port 1 and Port 2 ure - Supports RMII Interface and 50 MHz Reference Low Power Dissipation Clock Output - Full-Chip Software Power-Down (Register Con- - IGMP Snooping (IPv4) Support for Multicast figuration Not Saved) Packet Filtering - Energy-Detect Mode Support - IPv4/IPv6 QoS Support - Dynamic Clock Tree Shutdown Feature - MAC Filtering Function to Forward Unknown - Per Port Based Software Power-Save on PHY Unicast Packets to Specified Port (Idle Link Detection, Register Configuration Pre- Comprehensive Configuration Register Access served) - Serial Management Interface (SMI) to All Inter- - Voltages: Single 3.3V Supply with Internal 1.8V nal Registers LDO for 3.3V VDDIO - MII Management (MIIM) Interface to PHY Reg- - Optional 3.3V, 2.5V, and 1.8V for VDDIO isters - Transceiver Power 3.3V for VDDA 3.3 2 - High Speed SPI and I C Interface to All Internal Industrial Temperature Range: 40C to +85C Registers Available in a 48-Pin LQFP, Lead-Free Package - I/O Pins Strapping and EEPROM to Program Selective Registers in Unmanaged Switch Applications Mode - Control Registers Configurable on the Fly (Port- VoIP Phone Priority, 802.1p/d/q, AN) Set-Top/Game Box QoS/CoS Packet Prioritization Support Automotive - Per Port, 802.1p and DiffServ-Based Industrial Control - Re-Mapping of 802.1p Priority Field Per Port IPTV POF basis, Four Priority Levels SOHO Residential Gateway Proven Integrated 3-Port 10/100 Ethernet Switch Broadband Gateway/Firewall/VPN - 3rd Generation Switch with Three MACs and Integrated DSL/Cable Modem Two PHYs Fully Compliant with IEEE 802.3u Wireless LAN Access Point + Gateway Standard Standalone 10/100 Switch 2017 Microchip Technology Inc. DS00002335B-page 1KSZ8863MLL/FLL/RLL TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: