LAN9116 Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Reduced Power Modes Highlights - Numerous power management modes Member of LAN9118 Family optimized for - Wake on LAN* medium-high performance applications - Magic packet wakeup* Easily interfaces to most 32-bit and 16-bit embed- - Wakeup indicator event signal ded CPUs - Link Status Change Efficient architecture with low CPU overhead Single chip Ethernet controller Integrated PHY - Fully compliant with IEEE 802.3/802.3u stan- Supports audio & video streaming over Ethernet: dards 1-2 high-definition (HD) MPEG2 streams - Integrated Ethernet MAC and PHY - 10BASE-T and 100BASE-TX support Medium-high speed member of LAN9118 Family (all members are pin-compatible) - Full- and Half-duplex support - Full-duplex flow control - Backpressure for half-duplex flow control Target Applications - Preamble generation and removal Medium-range Cable, satellite, and IP set-top - Automatic 32-bit CRC generation and check- boxes ing Digital video recorders and DVD recorders/play- - Automatic payload padding and pad removal - Loop-back modes ers High definition televisions Flexible address filtering modes - One 48-bit perfect address Digital media clients/servers and home gateways - 64 hash-filtered multicast addresses Video-over IP Solutions, IP PBX & video phones - Pass all multicast Wireless routers & access points - Promiscuous mode - Inverse filtering Key Benefits - Pass all incoming with status report - Disable reception of broadcast packets Non-PCI Ethernet controller for medium-high per- Integrated Ethernet PHY formance applications - 32-bit interface - Auto-negotiation - Automatic polarity detection and correction - Burst-mode read support Eliminates dropped packets High-Performance host bus interface - Simple, SRAM-like interface - Internal buffer memory can store over 200 packets - 32/16-bit data bus - Large, 16Kbyte FIFO memory that can be - Supports automatic or host-triggered PAUSE allocated to RX or TX functions and back-pressure flow control - One configurable host interrupt Minimizes CPU overhead Miscellaneous features - Supports Slave-DMA - Low profile 100-pin, TQFP RoHS Compliant - Interrupt Pin with Programmable Hold-off package timer - Integral 1.8V regulator Reduces system cost and increases design flexi- - General Purpose Timer bility - Support for optional EEPROM - SRAM-like interface easily interfaces to most - Support for 3 status LEDs multiplexed with embedded CPUs or SoCs Programmable GPIO signals - Low-cost, low--pin count non-PCI interface 3.3V Power Supply with 5V tolerant I/O for embedded designs 0 to 70 C * Third-party brands and names are the property of their respective owners. 2005-2017 Microchip Technology Inc. DS00002268B-page 1LAN9116 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: