MA990002 Microchip

CEC1712 Cryptographic Embedded Controller - External 32 kHz crystal (XTAL) source Operating Conditions - External single-ended 32 kHz clock Operating Voltages: 3.3 V and 1.8 V source o o C to 85 C Operating Temperature Range: -40 Package Options Low Power Modes - 84 pin WFBGA Chip is designed to always operate in Lowest Security Features Power state during Normal Operation Supports all 5 ACPI Power States for PC plat- Boot ROM Secure Boot Loader forms - Hardware Root of trust using Secure Boot Supports 2 Chip-level Sleep Modes: Light Sleep and Immutable code using ECDSA P-384 and Heavy Sleep and SHA-384 - Low Standby Current in Sleep Modes - Supports 2 Code Images in external SPI Flash (Primary and Fall back image) ARM Cortex-M4 Embedded Processor - Authenticates SPI Flash image before load- Programmable clock frequency up to 48 MHz ing Fixed point processor - Support AES-256 Encrypted SPI Flash Single 4GByte Addressing Space images Nested Vectored Interrupt Controller (NVIC) - Key Revocation - Maskable Interrupt Controller - Roll back protection - Maskable hardware wake up events - DICE support - 8 Levels of priority, individually assignable by Hardware Accelerators: vector - Multi purpose AES Crypto Engine: EC Interrupt Aggregator expands number of Inter- - Support for 128-bit - 256-bit key length rupt sources supported or reduces number of vec- - Supports Battery Authentication applica- tors needed tions Standard debug support Complete ARM - Digital Signature Algorithm Support - JTAG-Based DAP port, comprised of SWJ- - Support for ECDSA and EC KCDSA DP and AHB-AP debugger access functions - Cryptographic Hash Engine Memory Components - Support for SHA-1, SHA-256 to SHA-512 - 256 KB Code/Data SRAM - Public Key Crypto Engine - 224 KB optimized for code performance - Hardware support for RSA and Elliptic - 32 KB optimized for data performance Curve asymmetric public key algorithms - 64 Bytes Battery Powered Storage SRAM - RSA keys length of 1024 to 4096 bits - 288 Bytes OTP - ECC Prime Field keys up to 571 bits - In circuit programmable - ECC Binary Field keys up to 571 bits -ROM - Microcoded support for standard public key algorithms - Contains Boot ROM - OTP for storing Keys and IDs - Contains Runtime APIs for built-in func- tions - Lockable on 32 B boundaries to prevent read access or write access Clocks - True Random Number Generator 48 MHz Internal PLL - 1 kbit FIFO 32 kHz Clock Sources - JTAG Disabled by default - Internal 32 kHz silicon oscillator 2020 Microchip Technology Inc. DS00003416B-page 1CEC1712 - 8 - Over voltage tolerant GPIO pins Peripheral Features - Glitch protection and Under-Voltage Protec- One Serial Peripheral Interface (SPI) Master Con- tion on all GPIO pins troller Input Capture and Compare timer - Dual and Quad I/O Support - Six 32-bit Capture Registers - Flexible Clock Rates - 11 Input Pins (ICTx) - Support for 1.8V and 3.3V slave devices - Full Crossbar switch allows any port to be - SPI Burst Capable connected to any capture register - SPI Controller Operates with Internal DMA - 32-bit Free-running timer Controller with CRC Generation - One 32-bit Compare Register output - Mappable to 2 ports (only 1 port active at a - Capture, Compare and Overflow Interrupts time) Universal Asynchronous Receiver Transmitter - SPI interface can be disabled after loading (UART) code - Three High Speed NS16C550A Compatible Internal DMA Controller UARTs with Send/Receive 16-Byte FIFOs - Hardware or Firmware Flow Control - UART1 - Configurable 2-pin/4-pin - Firmware Initiated Memory-to-Memory trans- - UART2 - 2-pin fers - UART3 - 2-pin - Hardware CRC-32 Generator on Channel 0 - Programmable Main Power or Standby - 12-Hardware DMA Channels support five Power Functionality SMBus Master/Slave Controllers and One SPI Controller - Standard Baud Rates to 115.2 Kbps, Custom Baud Rates to 1.5 Mbps I2C/SMBus Controllers Programmable Timer Interface - 5 I2C/SMBus controllers - Two16-bit Auto-reloading Timer Instances - 3 I2C only controllers without the Network layer - 16 bit Pre-Scale divider - 10 Configurable I2C ports - Halt and Reload control - Full Crossbar switch allows any port to be - Auto Reload connected to any controller - Two 32-bit Auto-reloading Timer Instances - Supports Promiscuous mode of operation - 16 bit Pre-Scale divider - Fully Operational on Standby Power - Halt and Reload control - Multi-Master Capable - Auto Reload - Supports Clock Stretching - Three Operating Modes per Instance: Timer - Programmable Bus Speeds (Reload or Free-Running) or One-shot. - 1 MHz Capable - Event Mode is not supported - Supports DMA Network Layer 32-bit RTOS Timer General Purpose I/O Pins - Runs Off 32kHz Clock Source - Inputs - Continues Counting in all the Chip Sleep States regardless of Processor Sleep State - Asynchronous rising and falling edge wakeup detection Interrupt High or Low - Counter is Halted when Embedded Controller Level is Halted (e.g., JTAG debugger active, break points) - Outputs: - Generates wake-capable interrupt event - Push Pull or Open Drain output Watch Dog Timer (WDT) - Programmable power well emulation - Generates an interrupt prior to resetting - Pull up or pull down resistor control 6 Programmable Pulse Width Modulator (PWM) - Automatically disabling pull-up resistors outputs when output driven low - Multiple Clock Rates - Automatically disabling pull-down resis- tors when output driven high - 16-Bit ON & 16-Bit OFF Counters - Programmable drive strength 2 Fan Tachometer Inputs - Two separate1.8V/3.3V configurable IO - 16 Bit Resolution regions Breathing LED Interface - Group or individual control of GPIO data - Two Blinking/Breathing LEDs DS00003416B-page 2 2020 Microchip Technology Inc.