MCP33131/21/11-XX 1 Msps/500 kSPS 16/14/12-Bit Single-Ended Input SAR ADC Features Typical Applications Sample Rate (Throughput): High-Precision Data Acquisition - MCP33131/21/11-10: 1 Msps Medical Instruments - MCP33131/21/11-05: 500 kSPS Test Equipment 16/14/12-Bit Resolution with No Missing Codes Electric Vehicle Battery Management Systems No Latency Output Motor Control Applications Wide Operating Voltage Range: Switch-Mode Power Supply Applications - Analog Supply Voltage (AV ): 1.8V DD Battery-Powered Equipment - Digital Input/Output Interface Voltage (DV ): IO 1.7V - 5.5V System Design Supports - External Reference (V ): 2.5V - 5.1V REF The MCP331x1-XX Evaluation Kit demonstrates the Pseudo-Differential Input Operation with performance of the MCP331x1-XX SAR ADC family Single-Ended Configuration: devices. The evaluation kit includes: (a) MCP331x1-XX - Input Full-Scale Range: 0V to +V REF Evaluation Board, (b) PIC32MZ EF Curiosity Board for Ultra Low Current Consumption (typical): data collection, and (c) SAR ADC Utility PC GUI. - During Input Acquisition (Standby): ~ 0.8 A Contact Microchip Technology Inc. for the evaluation - During Conversion: tools and the PIC32 MCU firmware example codes. MCP331x1-10: ~1.6 mA Package Types MCP331x1-05: ~1.4 mA V 1 10 DV SPI-Compatible Serial Communication: REF IO - SCLK Clock Rate: up to 100 MHz Top View MSOP-10 AV 2 9 SDI DD ADC Self-Calibration for Offset, Gain, and A + 3 8 SCLK IN Linearity Errors: A - 4 SDO 7 IN - During Power-Up (automatic) GND 5 6 CNVST - On-Demand via users command during normal operation V 1 10 DV REF IO AEC-Q100 Qualified: TDFN-10 AV Top View SDI 2 9 DD - Temperature Grade 1: -40C to +125C A + 3 8 SCLK IN Package Options: MSOP-10 and TDFN-10 A - 4 7 SDO IN GND 5 6 CNVST MCP331x1-XX Device Offering (Note 1): Performance (Typical) Sample Input Range Part Number Resolution Input Type SNR SFDR THD INL DNL Rate (dBFS) (dB) (dB) (LSB) (LSB) MCP33131-10 16-bit 1 Msps Single-Ended 0V to 5.1V 86.7 98.9 -97.4 2.2 0.9 MCP33121-10 14-bit 1 Msps Single-Ended 0V to 5.1V 83.5 98.8 -97.2 0.55 0.25 MCP33111-10 12-bit 1 Msps Single-Ended 0V to 5.1V 73.8 95.9 -93.7 0.12 0.06 MCP33131-05 16-bit 500 kSPS Single-Ended 0V to 5.1V 86.7 98.9 -97.4 2.2 0.9 MCP33121-05 14-bit 500 kSPS Single-Ended 0V to 5.1V 83.5 98.8 -97.2 0.55 0.25 MCP33111-05 12-bit 500 kSPS Single-Ended 0V to 5.1V 73.8 95.9 -93.7 0.12 0.06 Note 1: SNR, SFDR, and THD are measured with f = 10 kHz, V = -1 dBFS, V = 5.1V. IN IN REF 2018 Microchip Technology Inc. DS20006122A-page 1MCP33131/21/11-XX Application Diagram 2.5V to 5.1V 1.8V 1.7V to 5.5V V AV DV REF DD IO 22 A + IN Analog Input 1.7 nF (0V to V ) SDI REF MCP331x1-XX Host Device CNVST SCLK (PIC32MZ) A - IN SDO Ground Reference of GND Analog Input During Standby, most of the internal analog circuitry is Description shutdown in order to reduce current consumption. The MCP33131/MCP33121/MCP33111-10 and Typically, the device consumes less than 1 A during MCP33131/MCP33121/MCP33111-05 are Standby. A new conversion is started on the rising edge single-ended 16, 14, and 12-bit, single-channel 1 Msps of CNVST. When the conversion is complete and the and 500kSPS ADC family devices, respectively, host lowers CNVST, the output data is presented on featuring low power consumption and high SDO, and the device enters Standby to begin acquiring performance, using a successive approximation the next input sample. The user can clock out the ADC register (SAR) architecture. output data using the SPI-compatible serial clock during Standby. The device operates with a 2.5V to 5.1V external reference (V ), which supports a wide range of input REF The ADC system clock is generated by an internal full-scale range from 0V to V . The reference voltage REF on-chip clock, therefore the conversion is performed setting is independent of the analog supply voltage independent of the SPI serial clock (SCLK). (AV ) and is higher than AV The conversion output DD DD. This device can be used for various high-speed and is available through an easy-to-use simple SPI- high-accuracy analog-to-digital data conversion compatible 3-wire interface. applications, where design simplicity, low power, and The device requires a 1.8V analog supply voltage no output latency are needed. (AV ) and a 1.7V to 5.5V digital I/O interface supply DD The device is AEC-Q100 qualified for automotive voltage (DV ). The wide digital I/O interface supply IO applications and operates over the extended (DV ) range (1.7V-5.5V) allows the device to IO temperature range of -40C to +125C. The available interface with most host devices (Master) available in package options are Pb-free TDFN-10 and MSOP-10. the current industry such as the PIC32 microcontrollers, without using external voltage level shifters. When the device is first powered-up, it performs a self-calibration to minimize offset, gain and linearity errors. The device performance stays stable across the specified temperature range. However, when extreme changes in the operating environment, such as in the reference voltage, are made with respect to the initial conditions (e.g. the reference voltage was not fully settled during the initial power-up sequence), the user may send a recalibrate command anytime to initiate another self-calibration to restore optimum performance. When the initial power-up sequence is completed, the device enters a low-current input acquisition mode, where sampling capacitors are connected to the input pins. This mode is called Standby. DS20006122A-page 2 2018 Microchip Technology Inc.