MCP3914 3V Eight-Channel Analog Front End Features: Description: Eight Synchronous Sampling 24-Bit Resolution The MCP3914 is a 3V eight-channel Analog Front End Delta-Sigma Analog-to-Digital (A/D) Converters (AFE) containing eight synchronous sampling Delta- Sigma Analog-to-Digital Converters (ADC), eight PGAs, 94.5 dB SINAD, -107 dBc Total Harmonic th phase delay compensation block, low-drift internal volt- Distortion (THD) (up to 35 Harmonic), 112 dBFS SFDR for Each Channel age reference, Digital Offset and Gain Error Calibration registers, and high-speed 20 MHz SPI compatible serial Enables 0.1% Typical Active Power Measurement interface. Error Over a 10,000:1 Dynamic Range Advanced Security Features: The MCP3914 ADCs are fully configurable with features - 16-Bit Cyclic Redundancy Check (CRC) such as: 16/24-bit resolution, Oversampling Ratio (OSR) Checksum on All Communications for Secure from 32 to 4096, gain from 1x to 32x, independent Data Transfers shutdown and Reset, dithering and auto-zeroing. The - 16-Bit CRC checksum and Interrupt Alert for communication is largely simplified with 8-bit commands, including various continuous Read/Write modes and Register Map Configuration 16/24/32-bit data formats that can be accessed by the - Register Map Lock with 8-Bit Secure Key Direct Memory Access (DMA) of an 8, 16 or 32-bit MCU, 2.7V-3.6V AV , DV DD DD and with the separate Data Ready pin that can directly be Programmable Data Rate Up to 125 ksps: connected to an Interrupt Request (IRQ) input of an MCU. - 4 MHz Maximum Sampling Frequency The MCP3914 includes advanced security features to - 16 MHz Maximum Master Clock secure the communications and the configuration set- Oversampling Ratio Up to 4096 tings, such as a CRC-16 checksum on both serial data Ultra-Low Power Shutdown Mode with < 10 A outputs and static register map configuration. It also -122 dB Crosstalk Between Channels includes a register map lock through an 8-bit secure key Low-Drift 1.2V Internal Voltage Reference: 9 ppm/C to stop unwanted WRITE commands from processing. Differential Voltage Reference Input Pins The MCP3914 is capable of interfacing with a variety of High-Gain Programmable Gain Amplifier (PGA) voltage and current sensors, including shunts, Current on Each Channel (up to 32 V/V) Transformers, Rogowski coils and Hall effect sensors. Phase Delay Compensation with 1 s Time Resolution Package Type Separate Data Ready Pin for Easy Synchronization MCP3914 (5x5 UQFN*) Individual 24-Bit Digital Offset and Gain Error Correction for Each Channel High-Speed 20 MHz Serial Peripheral Interface 40 39 38 37 36 35 34 33 32 31 (SPI) with Mode 0,0 and 1,1 Compatibility CH2+ 1 30 SDI Continuous Read/Write Modes for Minimum CH2- 2 29 SDO Communication Time with Dedicated 28 CH3- 3 SCK 16/32-Bit Modes 27 CS CH3+ 4 Available in a 40-Lead UQFN Package 26 OSC2 NC 5 Extended Temperature Range: -40C to +125C EP 41 25 OSC1/CLKI NC 6 D 24 GND CH4+ 7 Applications: 23 NC CH4- 8 Polyphase Energy Meters 22 DR CH5- 9 Energy Metering and Power Measurement 21 D GND CH5+ 10 Automotive 11 12 13 14 15 16 17 18 19 20 Portable Instrumentation Medical and Power Monitoring Audio/Voice Recognition *Includes Exposed Thermal Pad (EP) see Table 3-1. 2013-2020 Microchip Technology Inc. DS20005216C-page 1 CH6+ CH1+ CH6- CH1- CH7- CH0- CH0+ CH7+ REFIN+/ A GND OUT AV DD REFIN- NC A GND DV DD AV DD D GND NC RESET DV DDMCP3914 Functional Block Diagram AV DV DD DD REFIN+/OUT Voltage AMCLK VREFEXT Xtal Oscillator Reference OSC1 MCLK Clock + Vref Generation DMCLK/DRCLK OSC2 - REFIN- Vref- Vref+ DMCLK OSR<2:0> OSR/2- OFFCAL CH0 GAINCAL CH0 PRE<1:0> PHASE1 <11:0> <23:0> <23:0> CH0+ + + X MOD<3:0> DATA CH0<23:0> CH0- - 3 PGA Phase SINC + Offset Gain 1 Modulator Shifter SINC Cal. Cal. OFFCAL CH1 GAINCAL CH1 <23:0> <23:0> OSR/2 CH1+ + + X MOD<7:4> DATA CH1<23:0> - CH1- 3 PGA Phase SINC + Offset Gain 1 Modulator Shifter SINC Cal. Cal. OSR/2- OFFCAL CH2 GAINCAL CH2 PHASE1 <23:12> <23:0> <23:0> CH2+ + + X MOD<11:8> DATA CH2<23:0> - CH2- 3 PGA Phase SINC + Offset Gain 1 Modulator Shifter SINC Cal. Cal. OFFCAL CH3 GAINCAL CH3 <23:0> <23:0> OSR/2 CH3+ + DR X + MOD<15:12> SDO DATA CH3<23:0> CH3- - 3 PGA Phase SINC + Offset Gain 1 Modulator Shifter SINC Cal. Cal. Digital SPI RESET OFFCAL CH4 GAINCAL CH4 Interface OSR/2- SDI <23:0> <23:0> PHASE0<11:0> SCK CH4+ + X + CS MOD<19:16> DATA CH4<23:0> CH4- - 3 PGA Phase SINC + Offset Gain 1 Modulator Shifter SINC Cal. Cal. OFFCAL CH5 GAINCAL CH5 <23:0> <23:0> OSR/2 CH5+ + X + MOD<23:20> DATA CH5<23:0> CH5- - 3 PGA Phase SINC + Offset Gain 1 Modulator Shifter SINC Cal. Cal. OSR/2- OFFCAL CH6 GAINCAL CH6 PHASE0<23:12> <23:0> <23:0> CH6+ + + X MOD<27:24> DATA CH6<23:0> CH6- - 3 PGA Phase SINC + Offset Gain 1 Modulator Shifter SINC Cal. Cal. OFFCAL CH7 GAINCAL CH7 <23:0> <23:0> OSR/2 CH7+ + + X MOD<31:28> DATA CH7<23:0> CH7- - 3 PGA Phase SINC + Offset Gain 1 Modulator Shifter SINC Cal. Cal. POR POR AV DV DD DD Monitoring Monitoring ANALOG DIGITAL AGND D GND DS20005216C-page 2 2013-2020 Microchip Technology Inc.