MEC152x
Keyboard and Embedded Controller for Notebook PC
- Supports Mode 0 and mode 3
Operating Conditions
-24MHz
Operating Voltages: 3.3 V and 1.8 V
o o
C to 85 C Clocks
Operating Temperature Range: -40
48 MHz Internal PLL
Low Power Modes
32 kHz Clock Sources
Chip is designed to always operate in Lowest
- Internal 32 kHz silicon oscillator
Power state during Normal Operation
- External 32 kHz crystal (XTAL) source
Supports all 5 ACPI Power States for PC plat-
forms - External single-ended 32 kHz clock
source
Supports 2 Chip-level Sleep Modes: Light Sleep
and Heavy Sleep
Package Options
- Low Standby Current in Sleep Modes
- 144 pin WFBGA
ARM Cortex-M4 Embedded Processor
- 128 pin VTQFP
Programmable clock frequency up to 48 MHz - 128 pin WFBGA
Fixed point processor
Security Features
Single 4GByte Addressing Space
Boot ROM Secure Boot Loader
Nested Vectored Interrupt Controller (NVIC)
- Hardware Root of Trust (RoT) using Secure
- Maskable Interrupt Controller
Boot and Immutable Code using ECDSA p-
- Maskable hardware wake up events
384 and SHA-384
- 8 Levels of priority, individually assignable by
- Supports 2 Code Images in external SPI
vector
Flash (Primary and Fall back image)
EC Interrupt Aggregator expands number of Inter-
- Supports Full EC firmware redundancy over
rupt sources supported or reduces number of vec-
Two Flash components
tors needed
- Authenticates SPI Flash image before load-
Standard debug support
Complete ARM
ing
- JTAG-Based DAP port, comprised of SWJ-
- Support AES-256 Encrypted SPI Flash
DP and AHB-AP debugger access functions
images
- Key Revocation
Memory Components
- Roll back protection up to 128 Revisions
- 256 KB Code/Data SRAM
Hardware Accelerators:
- 224 KB optimized for code performance
- Multi purpose AES Crypto Engine:
- 32 KB optimized for data performance
- Support for 128-bit - 256-bit key length
- 64 Bytes Battery Powered Storage SRAM
- Supports Battery Authentication applica-
-4K bits OTP
tions
- In circuit programmable
- Digital Signature Algorithm Support
-ROM
- Support for ECDSA and EC_KCDSA
- Contains Boot ROM
- Cryptographic Hash Engine
- Contains Runtime APIs for built-in func-
- Support for SHA-1, SHA-256 to SHA-512
tions
- Public Key Crypto Engine
- 2K byte Internal EEPROM (MEC1523 Only)
- Hardware support for RSA and Elliptic
- 4Mbit in-chip SPI Serial Flash (MEC1527
Curve asymmetric public key algorithms
only)
- RSA keys length of 1024 to 4096 bits
- SST25PF040C
- ECC Prime Field keys up to 571 bits
- SPI Master controller
2020 Microchip Technology Inc. DS00003427D-page 1MEC152x
- ECC Binary Field keys up to 571 bits
- SPI Burst Capable
- Microcoded support for standard public - SPI Controller Operates with Internal DMA
key algorithms Controller with CRC Generation
- OTP for storing Keys and IDs - Mappable to the following ports (only 1 port
active at a time)
- Lockable on 32 B boundaries to prevent
read access or write access - 1 shared SPI Interface
- True Random Number Generator - 1 Private SPI interface
- 1 kbit FIFO - 1 General Purpose SPI interface
- JTAG Disabled by default - 1 In-Chip SPI (MEC1527 Only)
8042 Emulated Keyboard Controller
System Host interface
- 8042 Style Host Interface
Enhanced Serial Peripheral Interface (eSPI)
- Port 92 Legacy A20M Support
- Intel eSPI Specification compliant
- Fast GATEA20 & Fast CPU_RESET
- eSPI Interface Base Spec, Intel Doc.
18 x 8 Interrupt Capable Multiplexed Keyboard
#327432-004, Rev. 1.0.MEC152x
Scan Matrix
- eSPI Compatibility Spec, Intel Doc.
- Optional Push-Pull Drive for Fast Signal
#562633, Rev. 0.6
Switching
- Support for Master Attached Flash Sharing
PECI Interface 3.1
(MAFS)
- Support Intels low voltage PECI
- Support for Slave Attached Flash Sharing
Port 80 BIOS Debug Port
(SAFS)
- Two Ports, Assignable to Any eSPI IO
- Supports all four channels:
Address
- Peripheral Channel
- 24-bit Timestamp with Adjustable Timebase
- Virtual Wires Channel
- 16-Entry FIFO
- Out-of-Band (OOB) Tunneled Message
Channel
Peripheral Features
- Run-time Flash Access Channel
Internal DMA Controller
- Supports EC Bus Master to Host Memory
- Hardware or Firmware Flow Control
- Supports up to 66 MHz maximum operating
- Firmware Initiated Memory-to-Memory trans-
frequency
fers
One Serial Peripheral Interface (SPI) Slave
- Hardware CRC-32 Generator on Channel 0
- Quad SPI (half-duplex) or Single wire (full
- 12-Hardware DMA Channels support five
duplex) support
SMBus Master/Slave Controllers and One
- Mode 0 and Mode3 operation
SPI Controller
- Programmable wait time for response delay
I2C/SMBus Controllers
System to EC Message Interface
- 5 I2C/SMBus controllers
- Two Embedded Memory Interfaces
- 3 I2C only controllers without the Network
- Provides Two Windows to On-Chip SRAM layer
for Host Access
- Up to 16 Configurable I2C ports
- Two Register Mailbox Command Interface
- Full Crossbar switch allows any port to be
- Mailbox Registers Interface connected to any controller
- Thirty-two 8-bit registers - Supports Promiscuous mode of operation
- Two Register Mailbox Command Inter- - Fully Operational on Standby Power
faces
- Multi-Master Capable
- Two Register SMI Source Interfaces
- Supports Clock Stretching
- Five ACPI Embedded Controller Interfaces
- Programmable Bus Speeds
- Four EC Interfaces
- 1 MHz Capable
- One Power Management Interface
- Supports DMA Network Layer
One Serial Peripheral Interface (SPI) Master Con-
General Purpose I/O Pins
troller
- Inputs
- Dual and Quad I/O Support
- Asynchronous rising and falling edge
- Flexible Clock Rates
wakeup detection Interrupt High or Low
- Support for 1.8V and 3.3V slave devices Level
DS00003427D-page 2 2020 Microchip Technology Inc.