MEC1704Q-C2-I/SZ

MEC170x Keyboard and Embedded Controller for Notebook PC GPIO and Core Logic supports 3.3V and 1.8V - Single byte read/write access - 32 Byte page size Operation. - 1,000,000 write cycle endurance Analog and PLL are 3.3V Operation only. LPC Interface ACPI Compliant - Supports LPC Bus frequencies of 19MHz to VTR (standby) and VBAT Power Planes 33MHz - Low Standby Current in Sleep Mode - 1.8V and 3.3V Support Configuration Register Set - LPC I/O Cycles Decoded - Compatible with ISA Plug-and-Play Standard - LPC Memory Cycles Decoded - EC-Programmable Base Address - Clock Run Support Cortex -M4 Processor Core ARM - Serial IRQ - 32-Bit ARM v7-M Instruction Set Architecture - ACPI SCI interface - Hardware Floating Point Unit (FPU) - SMI output - Single 4GByte Addressing Space (Von Neu- Enhanced Serial Peripheral Interface (eSPI) mann Model) - Intel eSPI Specification compliant - Little-Endian Byte Ordering - Supports four channels/interfaces: - Bit-Banding Feature Included - Peripheral channel Interface - NVIC Nested Vectored Interrupt Controller - Virtual Wire Interface - Up to 240 Individually-Vectored Interrupt Sources - Out of Band Channel Interface Supported - Flash Channel Interface - 8 Levels of Priority, Individually Assignable By Vector - Supports EC Bus Master to Host Memory - Chip-Level Interrupt Aggregator supported, to Legacy Support expand number of interrupt sources or reduce - Fast GATEA20 and Fast CPU RESET number of vectors System to EC Message Interface - System Tick Timer - 8042 Style Host Interface - Complete ARM-Standard Debug Support - JTAG-Based DAP Port, Comprised of SWJ-DP and - ACPI Embedded Controller Interface AHB-AP Debugger Access Functions - Five Instances - Full DWT Hardware Functionality: 4 Data - 1 or 4 Byte Data transfer capable Watchpoints and Execution Monitoring - Full-duplex Register Access - Full FPB Hardware Breakpoint Functionality: 6 - ACPI Power Management Interface Execution Breakpoints and 2 Literal (Data) - SCI Event-Generating Functions Breakpoints - Mailbox Registers Interface - Comprehensive ARM-Standard Trace Sup- - Thirty-two 8-Bit Scratch Registers port - Two Register Mailbox Command Interface - Full DWT Hardware Trace Functionality for - Two Register SMI Source Interface Watchpoint and Performance Monitoring - Three Embedded Memory Interface - Full ITM Hardware Trace Functionality for Instances Instrumented Firmware Support and Profiling - Host Serial or Parallel IRQ Source - Full ETM Hardware Trace Functionality for - Provides Two Windows to On-Chip SRAM for Host Instruction Trace Access - Full TPIU Functionality for Trace Output - Two Register Mailbox Command Interface Communication - Host Access of Virtual Registers Without EC - MPU Feature Intervention - 1S Delay Register Battery Backed Resources Internal Memory - Power-Fail Status Register - 64k Boot ROM - 32 KHz Clock Generator - Two blocks of SRAM, totaling 256KB, 320KB - Week Alarm Timer Interface or 480KB - Real Time Clock - Each block can be used for either program or data - VBAT-Powered Control Interface - One block 32KB or 64KB - Five Wake-up Input Signals - One block 224KB, 288KB or 416KB - Optional Latching of Wake-up Inputs - 128 Bytes Battery Powered SRAM - VBAT-Backed 128 Byte Memory - Non-volatile Read/Write Memory - 2KB of EEPROM 2016-2020 Microchip Technology Inc. DS00002206H-page 1MEC170x Four EC-based SMBus 2.0 Host Controllers - Up to 148 GPIOs - Allows Master or Dual Slave Operation - 8 GPIO Pass-Through Port (GPTP) - Fully Operational on Standby Power - Glitch protection on most GPIO pins 2 - DMA-driven I C Network Layer Hardware - 6 Battery-powered General Purpose Outputs 2 -I C Datalink Compatibility Mode - All GPIOs can be powered by 1.8V - Multi-Master Capable - Programmable Drive Strength and Slew Rate - Supports Clock Stretching on all GPIOs - Programmable Bus Speed up to 1MHz Programmable 16-bit Counter/Timer Interface - Hardware Bus Access Fairness Interface - Four 16-bit Auto-reloading Counter/Timer - SMBus Time-outs Interface Instances - AMD-TSI Port - Four Operating Modes per Instance: Timer, - 12 Ports Assignable to Any Controller One-shot, Event and Measurement - All ports 1.8V-capable - 4 External Inputs, 4 External Outputs Hibernation Timer Interface Five independent Hardware Driven PS/2 Ports - Two 32.768 KHz Driven 16-bit Timers - Three controllers - Programmable Wake-up from 0.5ms to 128 Minutes - Fully functional on Main and/or Suspend Power - One 32.768 KHz Driven 32-bit RTOS Timer - PS/2 Edge Wake Capable - Programmable Wake-up from 30S to 35 Hours - Two ports 5V tolerant - Auto Reload Option Two General Purpose Serial Peripheral Interface System Watch Dog Timer (WDT) Controllers (ECGP-SPI) Input Capture and Compare Timer - One 3-pin EC-driven Full Duplex Serial Com- - 32-bit Free-running timer munication Interface - Six 32-bit Capture Registers - Flexible Clock Rates - Two 32-bit Compare Registers - SPI Burst Capable - Capture, Compare and Overflow Interrupts One Quad Serial Peripheral Interface (SPI) Control- - Toggle Output on Compare Timers ler Week Timer - Master Only SPI Controller - Power-up Event Output - Mappable to two ports (only 1 port active at a - Week Alarm Interrupt with 1 Second to 8.5 Year time) Time-out - Dual and Quad I/O Support - Sub-Week Alarm Interrupt with 0.50 Seconds - - Flexible Clock Rates 72.67 hours time-out - SPI Burst Capable - 1 Second and Sub-second Interrupts - SPI Controller Operates with Internal DMA Real Time Clock (RTC) Controller with CRC Generation - VBAT Powered 18 x 8 Interrupt Capable Multiplexed Keyboard Scan - 32KHz Crystal Oscillator Matrix - Time-of-Day and Calendar Registers - Optional Push-Pull Drive for Fast Signal Switch- - Programmable Alarms ing - Supports Leap Year and Daylight Savings Time Four Breathing/Blinking LED Interfaces Two Microchip BC-Link Interconnection Bus - Supports three modes of operation: - Programmable Bus Clock Rate - Blinking Mode with Programmable Blink Rates PECI Interface 3.0 - Breathing LED Output FAN Support -8-bit PWM - Eleven Programmable Pulse-Width Modulator - Breathing LED Supports Piecewise-linear (PWM) Outputs Brightness Curves, Symmetric or Asymmetric - Multiple Clock Rates - Supports Low Power Operation in Blinking and - 16-Bit On and 16-Bit Off Counters Breathing Modes - Three Fan Tachometer Inputs - Operates on Standby Power - Two RPM-Based Fan Speed Controllers - Operates in Chip s Heavy Sleep State on 32kHz - Each includes one Tach input and one PWM output standby clock - 3% accurate from 500 RPM to 16k RPM - Operational in EC Sleep State - Automatic Tachometer feedback - Pin buffers capable of sinking up to 12 mA - Aging Fan or Invalid Drive Detection Three Resistor/Capacitor Identification Detection - Spin Up Routine (RC ID) ports - Ramp Rate Control - Single Pin Interface to External Inexpensive RC - RPM-based Fan Speed Control Algorithm Circuit ADC Interface - Replacement for Multiple GPIOs - 10-bit Conversion in 1 s - Provides 8 Quantized States on One Pin - 16 Channels General Purpose I/O Pins DS00002206H-page 2 2016-2020 Microchip Technology Inc.