PolarFire SoC Product Overview Overview PolarFire SoC is built upon the award-winning PolarFire FPGA non-volatile FPGA platform. Featuring a five core Linux capable processor subsystem based on the RISC-V ISA, PolarFire SoC brings to market an innovative, mid- range, embedded compute platform that inherits all the benefits of the PolarFire FPGA product family. The RISC-V CPU micro-architecture implementation is a simple, 5-stage single issue in order pipeline that does not suffer from the Meltdown and Spectre exploits found in common out-of-order machines. All five CPU cores are coherent with the memory subsystem allowing a versatile mix of deterministic real time systems and Linux in a single, multi-core CPU cluster. With Secure Boot built-in, innovative Linux and Real Time modes, a large Flexible L2 memory subsystem, and a rich set of embedded peripherals, PolarFire SoC provides designers new choices in secure, power-efficient, embedded compute platforms. This document describes the features of PolarFire SoC extended commercial (0 C to 100 C T ) and industrial (40 C to 100 C T ) device offerings. j j Microprocessor Subsystem Features 64-bit RV64GC Quad Application processing cores, Fmax of 667 MHz (40 C to 100 C T ), 3.125 CoreMarks/ j MHz, 1.714 DMIPS/MHz L1 memory subsystem with single-error correct, double-error detect (SECDED) 32 KB 8-way instruction cache or optional 28 Kbyes tightly integrated memory 32 KB 8-way data cache Memory Management Unit (MMU) Physical Memory Protection (PMP) unit 64-bit RV64IMAC monitor processor core, Fmax of 667 MHz (40 C to 100 C T ), 3.125 CoreMarks/MHz, j 1.714 DMIPS/MHz L1 memory subsystem with SECDED 16 KB 2-way instruction cache 8 KB scratch pad memory PMP unit Flexible 2 MB L2 memory subsystem with SECDED configurable as: 16-way set associative L2 cache with write-back policy Loosely Integrated Memory (LIM) mode for deterministic access Coherent directly addressable Scratchpad Memory mode for shared messages across cores Integrated 36-bit DDR4/DDR3/LPDDR4/LPDDR3 memory controller with SECDED DDR4 at 1.6 Gbps with a 8 GB address reach Cache coherent CPU bus matrix AMBA I/O switch with QoS and Memory Protection Unit (MPU) Integrated 128 KB embedded non-volatile memory (eNVM) for boot code Boot options Microchip secure boot User defined, PUF-protected secure boot Boot directly from eNVM Platform interrupt controller Overview DS60001656B-page 1 2021 Microchip Technology Inc. 185 interrupt sources from the microprocessor subsystem and FPGA fabric with seven priority levels Local interrupt controller 48 local interrupts sourced from the FPGA drive the local interrupt controller on each core Debug Ten hardware triggers per CPU (triggers can be configured as a breakpoint or a watchpoint) Instruction trace on all CPUs Performance counters Runtime-configurable AXI bus monitors Monitor AXI commands to DDR Monitor an AXI port going into or out of the AMBA I/O AXI switch 32-bit fabric monitor SmartDebug Dynamically monitor any two nets in the FPGA on two pins without changing the FPGA design Read/write to FPGA flip-flops and memories Halt clock trees, inspect logic tree FPGA breakpoints SmartDebug integrated into processor debug transport layerdebug from a single tool chain Secure debug remotely over Ethernet (both the processor subsystem and the FPGA design) Processor I/O Two GigE MACs One USB 2.0 OTG MMC 5.1 SD/SDIO Two CAN 2.0 A and B Execute in place Quad SPI flash controller Five multi-mode UARTs 2 Two SPI, two I C RTC, GPIO Five watchdog timers Timers Processor to FPGA Interconnect Two 64-bit processor-fabric bidirectional AXI4 interfaces One 64-bit fabric-to-processor AXI4 interface One 32-bit processor-to-fabric APB interface FPGA Features Up to 461k logic elements consisting of a 4-input look-up table (LUT) with a fractureable D-type flip-flop 20 Kb dual- or two-port large static random access memory (LSRAM) block with built-in SECDED 64 12 two-port RAM block implemented as an array of latches 18 18 math block with a pre-adder, a 48-bit accumulator, and an optional 16-deep 18 coefficient ROM Built-in PROM, modifiable at program time and readable at run time for user data storage High-speed serial connectivity with built-in, multi-gigabit, multi-protocol transceivers from 250 Mbps to 12.7 Gbps Integrated dual x4 PCIe Gen2 endpoint (EP) and root port (RP) designs High-speed I/O (HSIO) supporting up to 1600 Mbps DDR4, 1333 Mbps DDR3L, and 1333 Mbps LPDDR3/DDR3 memories with integrated I/O digital General-purpose I/O (GPIO) supporting 3.3 V, built-in CDR for serial gigabit Ethernet, 1067 Mbps DDR3, and 1250 Mbps LVDS I/O speed with integrated I/O digital logic Low-power, phase-locked loops (PLLs) and delay-locked loops (DLLs) for high precision and low jitter 1.0 V and 1.05 V operating modes DS60001656B-page 2 Overview 2021 Microchip Technology Inc.