ISO-CMOS MT093 8 x 12 Analog Switch Array Data Sheet September 2011 Features Internal control latches and address decoder Ordering Information Short set-up and hold times MT093AE1 40 Pin PDIP* Tubes Wide operating voltage: 4.5 V to 14.5 V MT093AP1 44 Pin PLCC* Tubes 3.5Vpp analog signal capability MT093APR1 44 Pin PLCC* Tubes R 65 max. V =14V, 25 C ON DD *Pb Free Matte Tin R 10 V =14V, 25 C ON DD 0 C to +70 C Full CMOS switch for low distortion Minimum feedthrough and crosstalk Description Low power consumption ISO-CMOS technology The Zarlink MT093 is fabricated in Zarlinks ISO- Applications CMOS technology providing low power dissipation and high reliability. The device contains a 8x12 array PBX systems of crosspoint switches along with a 7 to 96 line Mobile radio decoder and latch circuits. Any one of the 96 switches can be addressed by selecting the Test equipment /instrumentation appropriate seven input bits. The selected switch can Analog/digital multiplexers be turned on or off by applying a logical one or zero to the DATA input. Audio/Video switching STROBE DATA RESET VDD VSS 11 AX0 AX1 AX2 8 x 12 7 to 96 Xi I/O AX3 Switch Latches Decoder (i=0-11) Array AY0 AY1 96 96 AY2 Yi I/O (i=0-7) Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1997-2011, Zarlink Semiconductor Inc. All Rights Reserved.MT093 Data Sheet 1 40 Y3 VDD 2 39 AY2 Y2 3 38 RESET DATA 40 4 37 6 5 4 3 2 44 43 42 41 AX3 Y1 1 5 36 7 AX0 NC NC 39 NC 6 35 NC 8 NC Y0 38 NC 9 NC 7 34 NC X6 37 X0 10 8 33 36 X6 X0 XY X1 9 32 X8 11 35 X7 X1 X2 10 31 X9 12 34 X8 X2 X3 11 30 X10 13 33 X9 X3 X4 14 12 29 X11 32 X10 X4 X5 15 13 28 NC 31 X11 X5 NC 16 14 27 NC 30 NC NC NC 15 26 NC 29 17 Y7 NC NC 18 19 20 21 22 23 24 25 26 27 28 16 25 NC AY1 17 24 Y6 AY0 18 23 STROBE AX2 19 22 Y5 AX1 20 21 VSS Y4 40 PIN PLASTIC DIP 44 PIN PLCC Figure 2 - Pin Connections Change Summary Changes from the August 2005 issue to the September 2011 issue. Page Item Change 1 Ordering Information Removed leaded packages as per PCN notice. Pin Description Pin Name Description PDIP PLCC 11 Y3 Y3 Analog (Input/Output): this is connected to the Y3 column of the switch array. 22 AY2 Y2 Address Line (Input). 3 3 RESET Master RESET (Input): this is used to turn off all switches. Active High. 4,5 4,5 AX3,AX0 X3 and X0 Address Lines (Inputs). 6,7 6-8 NC No Connection. 8-13 9-14 X6-X11 X6-X11 Analog (Inputs/Outputs): these are connected to the X6-X11 rows of the switch array. 14 15-17 NC No Connection. 15 18 Y7 Y7 Analog (Input/Output): this is connected to the Y7 column of the switch array. 16 - NC No Connection. 17 19 Y6 Y6 Analog (Input/Output): this is connected to the Y6 column of the switch array. 2 Zarlink Semiconductor Inc. Y7 NC Y6 AX0 STROBE AX3 Y5 RESET VSS AY2 Y4 Y3 AX1 VDD AX2 Y2 AY0 DATA Y1 AY1 NC Y0