(Preliminary) PL123E-09 Low Skew Zero Delay Buffer FEATURES DESCRIPTION Frequency Range 10MHz to 220MHz The PL123E-09 (-09H for High Drive) is a high perfor- mance, low skew, low jitter zero delay buffer d esigned Zero input - output delay. to distribute high speed clocks. It has two low-skew Low Output to Output Skew output banks, of 4 outputs each, that are synchronized Optional Drive Strength: with the input. Control of the two banks of outputs is Standard (8mA) PL123E-09 achieved by using the S1 and S2 inputs as shown in High (12mA) PL123E-09H the Selector Definition table on page 2. 2.5V or 3.3V, 10% operation. Available in 16-Pin SOP or TSSOP packages The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than 100ps, the device acts as a zero delay buffer. The input output propaga- tion delay can be advanced or delayed by adjusting the load on the CLKOUT pin. These parts are not intended for 5V input-tolerant ap- plications. BLOCK DIAGRAM REF CLKOUT PLL Mux CLKA1 CLKA2 REF 1 16 CLKOUT CLKA1 2 15 CLKA4 CLKA3 CLKA2 3 14 CLKA3 CLKA4 VDD 4 13 VDD GND 5 12 GND CLKB1 CLKB1 6 11 CLKB4 S1 Selector CLKB2 7 10 CLKB3 CLKB2 Inputs S2 8 9 S1 S2 CLKB3 CLKB4 Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 12/13/11 Page 1 Bank B Bank A (Preliminary) PL123E-09 Low Skew Zero Delay Buffer PIN DESCRIPTIONS Package Type Name Type Description TSSOP-16L SOP-16L 1 REF 1 1 I Input reference frequency. 2 CLKA1 2 2 O Buffered clock output, Bank A 2 CLKA2 3 3 O Buffered clock output, Bank A VDD 4,13 4,13 P VDD connection GND 5,12 5,12 P GND connection 2 CLKB1 6 6 O Buffered clock output, Bank B 2 CLKB2 7 7 O Buffered clock output, Bank B 3 S2 8 8 I Selector input 3 S1 9 9 I Selector input 2 CLKB3 10 10 O Buffered clock output, Bank B 2 CLKB4 11 11 O Buffered clock output, Bank B 2 CLKA3 14 14 O Buffered clock output, Bank A 2 CLKA4 15 15 O Buffered clock output, Bank A 2 CLKOUT 16 16 O Buffered clock output. Internal feedback on this pin. Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. 3: Weak Pull-Up on S1 and S2 SELECTOR DEFINITION CLOCK A1 A4 CLOCK B1 B4 S2 S1 CLKOUT Output Source PLL Shutdown (Bank A) (Bank B) 0 0 Three-state Three-state Driven PLL N 0 1 Driven Three-state Driven PLL N 1 0 Driven Driven Driven Reference Y 1 1 Driven Driven Driven PLL N INPUT / OUTPUT SKEW CONTROL The PL123E-09 will achieve Zero Delay from input to output when all the outputs are loaded equally . Adjust- ments to the input/output delay can be made by adding additional loading to the CLKOUT pin. Please contact Micrel for more information. Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 12/13/11 Page 2