SCH5017 Super I/O with Temperature Sensing, Quiet Auto Fan and Glue Logic - Modem Control Circuitry Product Features - 480 Address and 15 IRQ Options General Features Infrared Port - 3.3 Volt Operation (SIO Block is 5 Volt Toler- - Multiprotocol Infrared Interface ant) - IrDA 1.0 Compliant - LPC Interface - SHARP ASK IR - Programmable Wake-up Event Interface - 480 Addresses, Up to 15 IRQ - PC99, PC2001 Compliant Multi-Mode Parallel Port with ChiProtect - ACPI 2.0 Compliant - Standard Mode IBM PC/XT, PC/AT, and - Multiplexed Command, Address and Data PS/2 Compatible Bi-directional Parallel Bus Port - Serial IRQ Interface Compatible with Serial- - Enhanced Parallel Port (EPP) Compatible - ized IRQ Support for PCI Systems EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) - PME Interface - IEEE 1284 Compliant Enhanced Capabilities - ISA Plug-and-Play Compatible Register Set Port (ECP) - 25 General Purpose Input/Output Pins - ChiProtect Circuitry for Protection - System Management Interrupt - 960 Address, Up to 15 IRQ and Three DMA AC Power Failure Recovery Options Watchdog Timer Keyboard Controller 2.88MB Super I/O Floppy Disk Controller - 8042 Software Compatible - Licensed CMOS 765B Floppy Disk Controller - 8 Bit Microcomputer - Software and Register Compatible with - 2k Bytes of Program ROM Microchip s Proprietary 82077AA Compatible - 256 Bytes of Data RAM Core - Four Open Drain Outputs Dedicated for Key- - Supports One Floppy Drive board/Mouse Interface - Configurable Open Drain/Push-Pull Output - Asynchronous Access to Two Data Registers Drivers and One Status Register - Supports Vertical Recording Format - Supports Interrupt and Polling Access - 16-Byte Data FIFO - 8 Bit Counter Timer - 100% IBM Compatibility - Port 92 Support - Detects All Overrun and Underrun Conditions - Fast Gate A20 and KRESET Outputs - Sophisticated Power Control Circuitry (PCC) Motherboard GLUE Logic Including Multiple Powerdown Modes for - IDE Reset Output Reduced Power Consumption - (4) Buffered PCI Reset Outputs with software - DMA Enable Logic controlled reset capability - default transpar- - Data Rate and Drive Control Registers ent - 480 Address, Up to Eight IRQ and Three - 3VSB Gate and 3V Gate signal generation DMA Options - Front Panel Reset Debouncing and Power - Support 3 Mode FDD Good Signal Generation Enhanced Digital Data Separator - Power Supply Turn On Circuitry with Support - 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 for power button on PS/2 Keyboard Kbps Data Rates - Resume Reset Signal Generation - Programmable Precompensation Modes - SMBus Isolation Circuitry (2 sets external Serial Ports and 1 set internal for Hardware Monitoring - Two Full Function Serial Ports Block) - High Speed NS16C550A Compatible UARTs - SMBus 2.0 compliant interface for Hardware with Send/Receive 16-Byte FIFOs Monitoring - Supports 230k and 460k Baud - LED Control (2) - Programmable Baud Rate Generator 2014 Microchip Technology Inc. DS00001781A-page 1SCH5017 Fan Control Description - 5 PWM (Pulse width Modulation) Outputs The SCH5017 is a 3.3V (Super I/O Block is 5V tolerant) - Two and three piece linear fan function PC99/PC2001 compliant Super I/O controller with an options. LPC interface. SCH5017 also includes Hardware Mon- - Low frequency and high frequency PWM itoring capabilities, enhanced Security features, Power support Control logic and Motherboard Glue logic. - 6 Fan Tachometer Inputs The SCH5017 s hardware monitoring capability - Programmable automatic fan control based includes temperature, voltage and fan speed monitor- on temperature - Interrupt Pin for out-of-limit Fantach Events ing. It has the ability to alert the system to out-of-limit conditions and automatically control the speeds of mul- - Fantach events generate PMEs and/or tiple fans. There are four analog inputs for monitoring Speaker warning external voltages of +5V, +5VTR, +12V and Vccp (core Temperature Monitor processor voltage), as well as internal monitoring of the - Monitoring of Two Remote Thermal Diodes SIO s VCC, VTR, and Vbat power supplies. The - Internal Ambient Temperature Measurement SCH5017 includes support for monitoring two external - Limit Comparison of all Monitored Values temperatures via thermal diode inputs and an internal - Interrupt Pin for out-of-limit Temperature Indi- sensor for measuring ambient temperature. The cation nHWM INT pin is implemented to indicate out-of-limit - Thermal events generate PMEs and/or temperature, voltage, and FANTACH conditions. The Speaker warning hardware monitoring block of the SCH5017 is accessi- - Configurable offset for internal or external ble via the System Management Bus (SMBus). The temperature channels. same interrupt event reported on the nHWM INT pin Voltage Monitor also creates PME wakeup events and speaker alarm - Monitor Power supplies (5V, +5VTR, +12V, annunciation. Vccp, Vbat, VTR, and VCC) The SCH5017 also allows for a two or three piece lin- - Limit Comparison of all Monitored Values ear fan function. - Interrupt Pin for out-of-limit Voltage Indication The Motherboard Glue logic includes various power - Voltage events generate PMEs and/or management and system logic including generation of Speaker warning nRSMRST, SMBus buffers, and buffered PCI reset out- Security Features puts. - Security Key Register (32 byte) for Device The SCH5017 incorporates complete legacy Super I/O Authentication functionality including an 8042 based keyboard and 6 VID (Voltage Identification) Inputs mouse controller, an IEEE 1284, EPP, and ECP com- Phoenix Keyboard BIOS ROM patible parallel port, one serial port that is 16C550A 128-Pin, QFP RoHS Compliant Package UART compatible, one IrDA 1.0 infrared ports, and a floppy disk controller with Microchip s true CMOS 765B core and enhanced digital data separator, The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures and is software and register compatible with Microchip s proprietary 82077AA core. System related functionality, which offers flexibility to the system designer, General Pur- pose I/O control functions, control of two LED s, and fan control using fan tachometer inputs and pulse width modulator (PWM) outputs. The SCH5017 is ACPI 1.0/2.0 compatible and there- fore supports multiple low power-down modes. It incor- porates sophisticated power control circuitry (PCC), which includes support for keyboard and mouse wake- up events. The SCH5017 supports the ISA Plug-and-Play Stan- dard register set (Version 1.0a). The I/O Address, DMA Channel and hardware IRQ of each logical device in the SCH5017 may be reprogrammed through the inter- nal configuration registers. There are up to 480 (960 - Parallel Port) I/O address location options, a Serialized IRQ interface, and Three DMA channels. DS00001781A-page 2 2014 Microchip Technology Inc.