Product Information

SST26VF064BT-104V/SM

SST26VF064BT-104V/SM electronic component of Microchip

Datasheet
NOR Flash 64Mbit SPISQI Flash 2.3V-3.6V 105C

Manufacturer: Microchip
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Price (USD)

1: USD 4.914 ea
Line Total: USD 4.91

3588 - Global Stock
Ships to you between
Thu. 30 May to Mon. 03 Jun
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
2402 - WHS 1


Ships to you between Thu. 30 May to Mon. 03 Jun

MOQ : 1
Multiples : 1
1 : USD 4.3189
25 : USD 4.2002
100 : USD 4.2002

     
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SST26VF064B / SST26VF064BA 2.5V/3.0V 64 Mbit Serial Quad I/O (SQI) Flash Memory Security ID Features - One-Time Programmable (OTP) 2 KByte, Secure ID Single Voltage Read and Write Operations - 64 bit unique, factory pre-programmed identifier - 2.7-3.6V or 2.3-3.6V - User-programmable area Serial Interface Architecture Temperature Range - Nibble-wide multiplexed I/Os with SPI-like serial - Industrial: -40C to +85C command structure - Industrial Plus: -40C to +105C - Mode 0 and Mode 3 Automotive AECQ-100 Grade 2 and Grade 3 - x1/x2/x4 Serial Peripheral Interface (SPI) Protocol Packages Available High Speed Clock Frequency - 8-contact WDFN (6mm x 5mm) - 2.7-3.6V: 104 MHz max - 8-contact WDFN (6mm x 8 mm) - 2.3-3.6V: 80 MHz max - 8-lead SOIJ (5.28 mm) Burst Modes - 16-lead SOIC (7.50 mm) - Continuous linear burst - 24-ball TBGA (6mm x 8mm) - 8/16/32/64 Byte linear burst with wrap-around All devices are RoHS compliant Superior Reliability - Endurance: 100,000 Cycles (min) Product Description - Greater than 100 years Data Retention The Serial Quad I/O (SQI) family of flash-memory Low Power Consumption: devices features a six-wire, 4-bit I/O interface that - Active Read current: 15 mA (typical 104 MHz) allows for low-power, high-performance operation in a - Standby Current: 15 A (typical) low pin-count package. SST26VF064B/064BA also Fast Erase Time support full command-set compatibility to traditional - Sector/Block Erase: 18 ms (typ), 25ms (max) Serial Peripheral Interface (SPI) protocol. System - Chip Erase: 35 ms (typ), 50 ms (max) designs using SQI flash devices occupy less board space and ultimately lower system costs. Page-Program - 256 Bytes per page in x1 or x4 mode All members of the 26 Series, SQI family are manufac- tured with proprietary, high-performance CMOS Super- End-of-Write Detection Flash technology. The split-gate cell design and thick- - Software polling the BUSY bit in status register oxide tunneling injector attain better reliability and man- Flexible Erase Capability ufacturability compared with alternate approaches. - Uniform 4 KByte sectors SST26VF064B/064BA significantly improve perfor- - Four 8 KByte top and bottom parameter mance and reliability, while lowering power consump- overlay blocks tion. These devices write (Program or Erase) with a - One 32 KByte top and bottom overlay block single power supply of 2.3-3.6V. The total energy con- - Uniform 64 KByte overlay blocks sumed is a function of the applied voltage, current, and Write-Suspend time of application. Since for any given voltage range, - Suspend Program or Erase operation to access the SuperFlash technology uses less current to pro- another block/sector gram and has a shorter erase time, the total energy consumed during any Erase or Program operation is Software Reset (RST) mode less than alternative flash memory technologies. Software Protection SST26VF064B/064BA are offered in 8-contact WDFN - Individual-Block Write Protection with permanent lock-down capability (6 mm x 5 mm or 6mm x 8mm), 8-lead SOIJ (5.28 mm), 16-lead SOIC (7.50 mm), and 24-ball TBGA. See Fig- - 64 KByte blocks, two 32 KByte blocks, and ure 2-2 for pin assignments. eight 8 KByte parameter blocks Two configurations are available upon order. - Read Protection on top and bottom 8 KByte parameter blocks SST26VF064B default at power-up has the WP and HOLD pins enabled, and the SIO2 and SIO3 pins dis- 2015-2019 Microchip Technology Inc. DS20005119J-page 1SST26VF064B / SST26VF064BA abled, to initiate SPI-protocol operations. enabled, to initiate Quad I/O operations. See I/O Con- SST26VF064BA default at power-up has the WP and figuration (IOC) on page 12 for more information about HOLD pins disabled, and the SIO2 and SIO3 pins configuring WP /HOLD and SIO3/SIO4 pins . TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

Tariff Desc

8542.32.00 32 No ..CMOS and MOS Read Only Memory and Programmable Read Only Memory whether erasable or non-erasable (for example, flash memory, EPROM, E2PROM, EAPROM, NOVRAM, ROM and PROM)
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