NOT RECOMMENDED FOR NEW DESIGNS SY10E111 Micrel, Inc. SY100E111 1:9 DIFFERENTIAL CLOCK SY10E111 SY100E111 DRIVER WITH ENABLE FEATURES DESCRIPTION Low skew The SY10/100E111 are low skew 1-to-9 differential drivers designed for clock distribution in new, high- Extended 100E V range of 4.2V to 5.5V EE performance ECL systems. They accept one differential or Guaranteed skew limits single-ended input, with V used for single-ended BB Differential design operation. The signal is fanned out to nine identical V output differential outputs. An enable input is also provided such BB that a logic HIGH disables the device by forcing all Q Enable input outputs LOW and all /Q outputs HIGH. Fully compatible with industry standard 10KH, 100K The device is specifically designed and produced for low I/O levels skew. The interconnect scheme and metal layout are 75K input pulldown resistors carefully optimized for minimal gate-to-gate skew within Fully compatible with ON Semiconductor the device. Wafer characterization and process control MC10E/100E111 ensure consistent distribution of propagation delay from lot to lot. Since the E111 shares a common set of basic Available in 28-pin PLCC package processing with the other members of the ECLinPS family, wafer characterization at the point of device personalization allows for tighter control of parameters, BLOCK DIAGRAM including propagation delay. To ensure that the skew specification is met, it is necessary that both sides of the differential output are Q0 terminated into 50 , even if only one side is being used. ln Q0 most applications, all nine differential pairs will be used and, therefore, terminated. In the case where fewer than Q1 nine pairs are used, it is necessary to terminate at least the Q1 output pairs on the same package side (i.e. sharing the same V as the pair(s) being used on that side) in order Q2 CCO to maintain minimum skew. Q2 The V output is intended for use as a reference BB voltage for single-ended reception of ECL signals to that Q3 device only. When using V for this purpose, it is BB Q3 recommended that V is decoupled to V via a 0.01 F BB CC capacitor. IN Q4 IN Q4 Q5 EN Q5 PIN NAMES Q6 Pin Function Q6 IN, /IN Differential Input Pair Q7 /EN Enable Input Q7 Q0, /Q0 Q8, /Q8 Differential Outputs Q8 V V Output BB BB V V to Output VBB Q8 CCO CC Rev.: E Amendment: /0 M9999-032006 1 Issue Date: March 2006 hbwhelp micrel.com or (408) 955-1690SY10E111 Micrel, Inc. SY100E111 PACKAGE/ORDERING INFORMATION (1) Ordering Information Package Operating Package Lead Part Number Type Range Marking Finish 25 24 23 22 21 20 19 SY10E111JI J28-1 Industrial SY10E111JI Sn-Pb VEE 26 18 Q3 (2) /EN SY10E111JITR J28-1 Industrial SY10E111JI Sn-Pb 27 17 /Q3 IN 28 16 Q4 SY100E111JI J28-1 Industrial SY100E111JI Sn-Pb PLCC VCC 1 VCCO TOP VIEW 15 (2) SY100E111JITR J28-1 Industrial SY100E111JI Sn-Pb /IN J28-1 /Q4 2 14 VBB 3 13 Q5 SY10E111JC J28-1 Commercial SY10E111JC Sn-Pb NC /Q5 4 12 (2) SY10E111JCTR J28-1 Commercial SY10E111JC Sn-Pb 56789 1011 SY100E111JC J28-1 Commercial SY100E111JC Sn-Pb (2) SY100E111JCTR J28-1 Commercial SY100E111JC Sn-Pb (3) SY10E111JY J28-1 Industrial SY10E111JY with Matte-Sn Pb-Free bar-line indicator 28-Pin PLCC (J28-1) (2, 3) SY10E111JYTR J28-1 Industrial SY10E111JY with Matte-Sn Pb-Free bar-line indicator (3) SY100E111JY J28-1 Industrial SY100E111JY with Matte-Sn Pb-Free bar-line indicator (2, 3) SY100E111JYTR J28-1 Industrial SY100E111JY with Matte-Sn Pb-Free bar-line indicator Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC Electricals only. A 2. Tape and Reel. 3. Pb-Free package is recommended for new designs. TIMING DIAGRAMS IN IN IN /IN /IN /IN ts tH tr /EN /EN 50% 50% 50% /EN 75 mV 75 mV /Q /Q /Q Q Q Q 75 mV 75 mV Figure 1. Set-up Time Figure 2. Hold Time Figure 3. Release Time M9999-032006 2 hbwhelp micrel.com or (408) 955-1690 Q0 /Q8 Q8 /Q0 /Q7 Q1 VCCO VCCO Q7 /Q1 /Q6 Q2 Q6 /Q2