Product Information

SY100E196JY

SY100E196JY electronic component of Microchip

Datasheet
Microchip Technology Micrel Delay Lines Timing Elements

Manufacturer: Microchip
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



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Obsolete
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0 - Global Stock

MOQ : 114
Multiples : 114

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SY100E196JY
Microchip

114 : USD 6.5544
1026 : USD 6.5423
N/A

Obsolete
     
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NOT RECOMMENDED FOR NEW DESIGNS Precision Edge SY10E196 Precision Edge Micrel, Inc. SY100E196 PROGRAMMABLE DELAY SY10E196 CHIP WITH ANALOG INPUT SY100E196 DESCRIPTION FEATURES Up to 2ns delay range The SY10/100E196 are programmable delay chips (PDCs) designed primarily for very accurate differential Extended 100E VEE range of 4.2V to 5.5V ECL input edge placement applications. 20ps digital step resolution The delay section consists of a chain of gates and a Linear input for tighter resolution linear ramp delay adjustment organized as shown in the >1GHz bandwidth logic diagram. The first two delay elements feature gates that have been modified to have delays 1.25 and 1.5 On-chip cascade circuitry times the basic gate delay of approximately 80ps. These 75Kk input pulldown resistor two elements provide the E196 with a digitally-selectable Fully compatible with Motorola MC10E/100E196 resolution of approximately 20ps. The required device Available in 28-pin PLCC package delay is selected by the seven address inputs D 0:6 , which are latched on-chip by a high signal on the latch enable (LEN) control. If the LEN signal is either LOW or left floating, then the latch is transparent. The FTUNE input takes an analog coltage and applies it to an internal linear ramp for reducing the 20s resolution still further. The FTUNE input is what differentiates the E196 from the E195. An eighth latched input, D7, is provided for cascading multiple PDCs for increased programmable range. The cascade logic allows full control of multiple PDCs, at the expense of only a single added line to the data bus for each additional PDC, without the need for any external gating. PIN NAMES Pin Function IN/IN Signal Input EN Input Enable D 0:7 Mux Select Inputs Q/Q Signal Output LEN Latch Enable SET MIN Minimum Delay Set SET MAX Maximum Delay Set CASCADE Cascade Signal FTUNE Linear Voltage Input VCCO VCC to Output Rev.: H Amendment: /0 M9999-032006 1 Issue Date: March 2006 hbwhelp micrel.com or (408) 955-1690 Precison Edge SY10E196 Micrel, Inc. SY100E196 PACKAGE/ORDERING INFORMATION (1) Ordering Information Package Operating Package Lead 25 24 23 22 21 20 19 Part Number Type Range Marking Finish D1 26 18 FTUNE SY10E196JC J28-1 Commercial SY10E196JC Sn-Pb D0 27 17 NC (2) SY10E196JCTR J28-1 Commercial SY10E196JC Sn-Pb LEN 28 16 VCC TOP VIEW SY100E196JI J28-1 Industrial SY100E196JI Sn-Pb VEE 1 PLCC 15 VCCO J28-1 IN 2 14 Q (2) SY100E196JITR J28-1 Industrial SY100E196JI Sn-Pb IN 3 13 Q (3) SY10E196JZ J28-1 Commercial SY10E196JZ with Matte-Sn VBB 4 12 VCCO Pb-Free bar-line indicator 56 7 8 9 10 11 (2, 3) SY10E196JZTR J28-1 Commercial SY10E196JZ with Matte-Sn Pb-Free bar-line indicator (3) SY100E196JY J28-1 Industrial SY100E196JY with Matte-Sn Pb-Free bar-line indicator (2, 3) SY100E196JYTR J28-1 Industrial SY100E196JY with Matte-Sn 28-Pin PLCC (J28-1) Pb-Free bar-line indicator Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC Electricals only. A 2. Tape and Reel. 3. Pb-Free package is recommended for new designs. M9999-032006 2 hbwhelp micrel.com or (408) 955-1690 NC D2 D3 NC EN D4 D5 SET MIN SET MAX D6 D7 CASCADE CASCADE NC

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8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
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