Product Information

SY100EP196VTG

Hot SY100EP196VTG electronic component of Microchip

Datasheet
Delay Lines / Timing Elements 3.3V/5V 2.5 GHz Programmable Delay Line w/Fine Tune
Manufacturer: Microchip
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 12.2145 ea
Line Total: USD 12.21

10 - Global Stock
Ships to you between
Thu. 09 May to Wed. 15 May
MOQ: 1  Multiples: 1
Pack Size: 1

 More Buying Options & Price Grid(s)

Availability Price Quantity
10 - WHS 1


Ships to you between Thu. 09 May to Wed. 15 May

MOQ : 1
Multiples : 1

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SY100EP196VTG
Microchip

1 : USD 12.2145
25 : USD 12.2145
100 : USD 12.2145

629 - WHS 2


Ships to you between Wed. 15 May to Fri. 17 May

MOQ : 1
Multiples : 1

Stock Image

SY100EP196VTG
Microchip

1 : USD 16.376
25 : USD 14.0415
100 : USD 12.7765

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Additional Infomation About Product

SY100EP196V 3.3V/5V 2.5 GHz Programmable Delay Chip with Fine Tune Control Features General Description Pin-for-Pin, Plug-In Compatible with the ON The SY100EP196V is a programmable delay line, Semiconductor MC100EP196 varying the time a logic signal takes to traverse from IN to Q. This delay can vary from about 2.2 ns to about Maximum Frequency >2.5 GHz 12.2 ns. The input can be PECL, LVPECL, NECL, or Programmable Range: 2.2 ns to 12.2 ns LVNECL. 10 ps Increments The delay varies in discrete steps based on a control 30 ps Fine Tuning Range word presented to SY100EP196V. The 10-bit width of = 3.0V to PECL Mode Operating Range: V CC this latched control register allows for delay increments 5.5V with V = 0V EE of approximately 10ps. In addition, delay may be = 0V with V NECL Mode Operating Range: V CC EE varied continuously in about a 30 ps range by setting = 3.0V to 5.5V the voltage at the FTUNE pin. Open Input Default State An eleventh control bit allows the cascading of multiple Safety Clamp on Inputs SY100EP196V devices, for a wider delay range. Each A Logic High on the /EN Pin will Force Q to Logic additional SY100EP196V effectively doubles the delay Low range available. D 0:10 can Accept Either ECL, CMOS, or TTL For maximum flexibility, the control register interface Inputs accepts CMOS or TTL level signals, as well as the input V Output Reference Voltage level at the IN and /IN pins. BB Available in a 32-Lead TQFP Package Package Type Applications SY100EP196V Clock Deskewing 32-Pin TQFP Timing Adjustment (Top View) Aperture Centering 32 31 30 29 28 27 26 25 VEE D8 1 24 2 23 D9 D0 3 22 D10 VCC 4 21 IN Q 5 20 /Q /IN 6 19 VCC VBB VCC VEF 7 18 8 17 FTUNE VCF 9 10111213141516 2021 Microchip Technology Inc. DS20006520A-page 1 D7 VEE D6 LEN SETMIN D5 SETMAX D4 VEE VCC D3 /CASCADE D2 CASCADE D1 /ENSY100EP196V Typical Applications Circuit Data Signal D Q+ of Unknown Phase Flip-Flop SY100EP196V CLOCK+ IN Q CK Q /IN CLOCK Fine Tune Voltage FTUNE /Q D 9:0 CONTROL LOGIC Functional Block Diagram DS20006520A-page 2 2021 Microchip Technology Inc.

HS Compliance

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits

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