SY100EL29V 5V/3.3V Dual Differential Data and Clock D Flip-Flop with Set and Reset Features General Description 3.3V and 5V Power Supply Option The SY100EL29V is a dual differential register with differential data (inputs and outputs) and clock. The Differential D, CLK and Q registers are triggered by a positive transition of the Extended V Range of 3.0V to 5.5V EE positive clock (CLK) input. A HIGH on the Reset (Rx) VBB Output for Single-Ended Use asynchronously resets the appropriate register so that 1 100 MHz Min. Toggle Frequency the Q outputs go LOW. A HIGH on the Set (Sx) Asynchronous Reset and Set asynchronously resets the appropriate register so that the Q outputs go HIGH. The Set and Reset inputs Available in 20-Pin SOIC Package cannot both be HIGH simultaneously. The differential input structures are clamped so that the inputs of unused registers can be left open without Package Type upsetting the bias network of the devices. The SY100EL29V clamping action will assert the /D and the /CLK sides of 20-Lead SOIC (Z) the inputs. The non-inverting input will pull down to V EE and the inverting input will be biased around V /2. VCC /Q0 S0 S1 VCC Q1 /Q1 VEE CC R0 Q0 Because of the edge-triggered flip-flop nature of the 20 19 18 17 16 15 14 13 12 11 devices, simultaneously opening both the clock and data inputs will result in an output which reaches an QQ QQ unidentified but valid state. R S S R D The fully differential design of the devices makes them D CLK CLK ideal for very high frequency applications where a registered data path is necessary. 1 2 3 4 5 6 7 8 9 10 /D0 /CLK0 VBB D1 /D1 CLK1 /CLK1 R1 D0 CLK0 2019 Microchip Technology Inc. 1DS20006241A-page SY100EL29V 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings PECL Power Supply Voltage (V ) ( Note 1).............................................................................................................. +8V CC NECL Power Supply Voltage (V ) ( Note 2) .............................................................................................................. 8V EE PECL Mode Input Voltage (V ) (Note 3) ................................................................................................................... +6V IN NECL Mode Input Voltage (V ) (Note 4) ................................................................................................................... 6V IN Continuous Output Current (I ).......................................................................................................................... 50 mA OUT Surge Output Current (I ) ................................................................................................................................ 100 mA OUT Stresses above those listed under Absolute Maximum ratings may cause permanent damage to the Notice: device. Exposure to maximum rating conditions for extended periods may affect device reliability. = 0V. Note 1: V EE = 0V. 2: V CC = 0V, V V . 3: V EE IN CC = 0V, V V . 4: V CC IN EE DC ELECTRICAL CHARACTERISTICS Electrical Characteristics: V = 3.0V to 5.5V, V = 0V or V = -5.5V to -3.0V, V = 0V CC EE EE CC T = 40C to +85C, unless otherwise stated. (Note 1) A Parameter Symbol Min. Typ. Max. Units Conditions 30 50 T = +25C A Power Supply Current I mA = 40C, 0C, EE T A 50 +85C V 1.085 V 1.005 V 0.88 T = 40C CC CC CC A Output High Voltage ( Note 2) V V OH 1.025 V 0.955 V 0.88 T = 0C to +85C V CC CC CC A V 1.830 V 1.695 V 1.555 T = 40C CC CC CC A Output Low Voltage ( Note 2) V V OL 1.810 V 1.705 V 1.620 T = 0C to +85C V CC CC CC A Input High Voltage V V 1.165 V 0.880 V IH CC CC (Single-Ended) Input Low Voltage V V 1.810 V 1.475 V IL CC CC (Single-Ended) V 1.38 V 1.26 V Output Reference Voltage V BB CC CC = 40C, T A V + 1.3 V 0.4 EE CC V < 500 mV PP = 0C to 85C, T A V + 1.2 V 0.4 EE CC V < 500 mV Common Mode Range PP V V IHCMR ( Note 3) = 40C, T A V + 1.5 V 0.4 EE CC V 500 mV PP = 0C to 85C, T A V + 1.4 V 0.4 EE CC V 500 mV PP 150 A Input High Current I IH 0.5 A D, CLK, R, S Input Low Current I IL 300 A /D, /CLK Note 1: Devices are designed to meet the DC specifications shown in the above table after thermal equilibration The circuit is in a test socket or mounted on a printed circuit board and transverse has been established. airflow greater than 500 lfpm is maintained. 2: Outputs are terminated through a 50 resistor to V 2.0V. CC 3: The CMR range is referenced to the most positive side of the differential input voltage. Normal operation is obtained if the high level falls within the specified range and the peak-to-peak voltage lies between 150 mV and 1V. DS20006241A-page 2 2019 Microchip Technology Inc.