NOT RECOMMENDED FOR NEW DESIGNS Precision Edge Micrel, Inc. 2/4, 4/5/6 CLOCK SY100S839V Precision Edge GENERATION CHIP SY100S839V FEATURES 3.3V and 5V power supply option 50ps output-to-output skew Precision Edge 50% duty cycle outputs Synchronous enable/disable DESCRIPTION Master Reset for synchronization Internal 75K input pull-down resistors The SY100S839V is a low skew 2/4, 4/5/6 clock generation chip designed explicitly for low skew clock Available in 20-pin SOIC package generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL/LVECL or, if positive power supplies are used, PECL/LVPECL input signal. In addition, by using the VBB output, a sinusoidal source can be AC-coupled into the device. If a single- ended input is to be used, the VBB output should be connected to the /CLK input and bypassed to ground via a 0.01 F capacitor. The VBB output is designed to act as the switching reference for the input of the S839V under single-ended input conditions. As a result, this pin can only source/sink up to 0.5mA of current. The common enable (/EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start-up, the internal flip-flops will attain a random state the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one S839V, the MR pin need not be exercised as the internal divider designs ensures synchronization between the 2/4, and the 4/5/6 outputs of a single device. Precision Edge is a registered trademark of Micrel, Inc. Rev.: B Amendment: /0 M9999-032206 1 Issue Date: March 2006 hbwhelp micrel.com or (408) 955-1690 Precision Edge Micrel, Inc. SY100S839V PACKAGE/ORDERING INFORMATION Ordering Information Package Operating Package Lead VCC 1 20 VCC Part Number Type Range Marking Finish /EN 2 19 Q0 SY100S839VZC Z20-1 Commercial SY100S839VZC Sn-Pb DIVSELb0 3 18 /Q0 (1) CLK 4 17 Q1 SY100S839VZCTR Z20-1 Commercial SY100S839VZC Sn-Pb (2) /CLK 5 16 /Q1 SY100S839VZG Z20-1 Industrial SY100S839VZG with Pb-Free VBB 6 15 Q2 Pb-Free bar-line indicator NiPdAu (1, 2) MR 7 14 /Q2 SY100S839VZGTR Z20-1 Industrial SY100S839VZG with Pb-Free Pb-Free bar-line indicator NiPdAu VCC 8 13 Q3 DIVSELb1 9 12 /Q3 Notes: 1. Tape and Reel. DIVSELa 10 11 VEE 2. Pb-Free package is recommended for new designs. 20-Pin SOIC (Z20-1) TRUTH TABLE PIN NAMES CLK /EN MR Function Pin Function Z L L Divide CLK Differential Clock Inputs ZZ H L Hold Q03 /EN Synchronous Enable X X H Reset Q03 MR Master Reset Note: VBB Reference Output Z = LOW-to-HIGH transition Q0, Q1 Differential 2/4 Outputs ZZ = HIGH-to-LOW transition Q2, Q3 Differential 4/5/6 Outputs DIVSELa Q0, Q1 OUTPUTS DIVSEL Frequency Select Input 0 Divide by 2 1 Divide by 4 DIVSELb1 DIVSELb0 Q2, Q3 OUTPUTS 0 0 Divide by 4 0 1 Divide by 6 1 0 Divide by 5 1 1 Divide by 5 M9999-032206 2 hbwhelp micrel.com or (408) 955-1690