Precision Edge 3.3V 1GHz DUAL 1:10 PRECISION MicreL, Inc. SY89828L Precision Edge LVDS FANOUT BUFFER/ SY89828L TRANSLATOR WITH 2:1 INPUT MUX FEATURES High-performance dual 1:10, 1GHz LVDS fanout Precision Edge buffer/translator Two banks of 10 differential LVDS outputs DESCRIPTION Guaranteed AC parameters over temperature and voltage: The SY89828L is a precision fanout buffer with 20 > 1GHz f MAX differential LVDS (Low Voltage Differential Swing) output < 50ps within device skew pairs. The part is designed for use in low voltage 3.3V < 400ps t , t time r f applications that require a large number of outputs to drive Each bank includes a 2:1 input mux precisely aligned, ultra low-skew signals to their destination. 2:1 mux input accepts LVDS and LVPECL The input is multiplexed from either LVDS or LVPECL (Low Low jitter performance Voltage Positive Emitter Coupled Logic) by the CLK SEL1 < 1ps cycle-to-cycle jitter and CLK SEL2 pins. The Output Enables (OE1 and OE2) RMS < 1ps total jitter are synchronous so that the outputs will only be enabled/ PP disabled when they are already in the LOW state. This 3.3V supply voltage avoids any chance of generating a runt clock pulse when Output enable function the device is enabled/disabled as can happen with an LVDS input includes internal 100 termination asynchronous control. Available in a 64-Pin EPAD-TQFP The SY89828L features a low pin-to-pin skew of less than 50psperformance previously unachievable in a standard product having such a high number of outputs. APPLICATIONS The SY89828L is available in a single space saving package, enabling a lower overall cost solution. Enterprise networking High-end servers Communications TYPICAL APPLICATION CIRCUIT 100 5 Primary Clock Source LVDS CLKA Primary 5 Card /LVDS CLKA Backup Clock Source 100 5 LVDS CLKB Redundant /LVDS CLKB 5 Card SEL1 Primary/Backup Clock Select (Switchover with 2.0ns) System using SY89828L as a switchover circuit from a Primary Clock to a Redundant backup Clock in a fail-safe application. LVPECL inputs not shown in this application. Precision Edge is a registered trademark of Micrel, Inc. Rev.: D Amendment: /0 M9999-012208 1 Issue Date: January 2008 hbwhelp micrel.com or (408) 955-1690 Precision Edge Micrel, Inc. SY89828L PACKAGE/ORDERING INFORMATION (1) Ordering Information 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Package Operating Package Lead Part Number Type Range Marking Finish SEL2 1 48 GNDO 47 Q7 LVDS CLKB 2 (2) /LVDS CLKB 3 46 /Q7 SY89828LHI H64-1 Industrial SY89828LHI Sn-Pb 45 Q8 VCCI 4 LVDS CLKA 44 /Q8 (2) 5 SY89828LHITR H64-1 Industrial SY89828LHI Sn-Pb 43 Q9 /LVDS CLKA 6 CLK SEL1 42 /Q9 7 (2) SY89828LHY H64-1 Industrial SY89828LHY with Pb-Free 41 VCCO LVPECL CLKA 8 /LVPECL CLKA 40 VCCO 9 Pb-Free bar-line indicator Matte-Sn 39 Q10 GNDI 10 38 /Q10 OE1 11 (2) 37 Q11 SY89828LHYTR H64-1 Industrial SY89828LHY with Pb-Free LVPECL CLKB 12 36 /Q11 /LVPECL CLKB 13 Pb-Free bar-line indicator Matte-Sn 35 Q12 CLK SEL2 14 34 /Q12 OE2 15 33 Notes: SEL1 16 GNDO 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC electricals only. A 2. Pb-Free package recommended for new designs. 64-Pin TQFP (H64-1) FUNCTIONAL BLOCK DIAGRAM 100 termination internal CLK SEL1 SEL1 OE1 LVDS CLKA 0 /LVDS CLKA 0 10 Q0 Q9 LVPECL CLKA 1 10 /Q0 /Q9 /LVPECL CLKA 1 LEN Q 100 termination internal D LVDS CLKB 0 0 10 /LVDS CLKB Q10 Q19 10 /Q10 /Q19 1 LVPECL CLKB LEN Q 1 /LVPECL CLKB D CLK SEL2 SEL2 OE2 M9999-012208 2 hbwhelp micrel.com or (408) 955-1690 VCCO VCCO /Q19 Q0 Q19 /Q0 /Q18 Q1 /Q1 Q18 /Q17 Q2 /Q2 Q17 /Q16 Q3 /Q3 Q16 Q4 /Q15 /Q4 Q15 Q5 /Q14 /Q5 Q14 Q6 /Q13 Q13 /Q6 VCCO VCCO