SY89833AL 3.3V Low-Noise, Ultra-Precision 1:4 LVDS Fanout Buffer/Translator with Internal Termination Features General Description Ultra-Low Jitter Design: The SY89833AL is a lower noise version of the SY89833L 3.3V, high-speed 2GHz differential, low -80fs Additive Phase Jitter (typical) RMS voltage differential swing (LVDS) 1:4 fanout buffer Guaranteed AC Performance Over Temperature optimized for ultra-low skew applications. Within device and Voltage: skew is guaranteed to be less than 20 ps over supply - DC-to > 2 GHz throughput voltage and temperature. - <470 ps Propagation Delay (IN-to-Q) The differential input buffer has a unique internal - <20 ps Within-Device Skew termination design that allows access to the - <190 ps Rise/Fall Times termination network through a V pin. This feature T Pin Accepts DC- Unique Input Termination and V allows the device to easily interface to different logic T and AC-Coupled Inputs reference is included for standards. A V REF-AC AC-coupled applications. High-Speed LVDS Outputs 3.3V Power Supply Operation The SY89833AL is part of Microchips high-speed clock Industrial Temperature Range: 40C to +85C synchronization family. For 2.5V applications, the SY89832U provides similar functionality while Available in 16-Pin (3 mm 3 mm) QFN Package operating from a 2.5V 5% supply. For applications that Applications require a different I/O combination, consult the Microchip website and choose from a comprehensive Processor Clock Distribution product line of high-speed, low-skew fanout buffers, SONET Clock Distribution translators, and clock generators. Fibre Channel Clock Distribution Gigabit Ethernet Clock Distribution Package Type SY89833AL 3x3 QFN (M) 16 15 14 13 1 12 Q1 IN /Q1 2 11 VT 3 10 VREF-AC Q2 4 /Q2 9 /IN 5 6 7 8 United States Patent No. RE44,134 2018 Microchip Technology Inc. DS20005608A-page 1 Q3 /Q0 /Q3 Q0 VCC VCC EN GNDSY89833AL Functional Block Diagram 1:4 Q0 /Q0 Q1 IN /Q1 50 VT 50 /IN Q2 VREF-AC /Q2 EN DQ (LVTTL/CMOS) Q3 /Q3 DS20005608A-page 2 2018 Microchip Technology Inc.