SY89874U 2.5 GHz, Any Differential In-to-LVPECL, Programmable Clock Divider/Fanout Buffer with Internal Termination Features General Description Integrated Programmable Clock Divider and 1:2 This low-skew, low-jitter device is capable of accepting Fanout Buffer a high-speed (e.g., 622 MHz or higher) CML, LVPECL, LVDS, or HSTL clock input signal and dividing down the Guaranteed AC Performance over Temperature frequency using a programmable divider ratio to create and Voltage: a frequency-locked, lower speed version of the input ->2.5 GHz f MAX clock. Available divider ratios are 2, 4, 8, and 16, or - <250 ps t /t r f straight pass-through. In a typical 622MHz clock - <15 ps Within-Device Skew system this would provide availability of 311MHz, Low Jitter Design: 155MHz, 77MHz, or 38MHz auxiliary clock components. -<10ps Total Jitter PP -<1ps Cycle-to-Cycle Jitter The differential input buffer has a unique internal RMS termination design that allows access to the Pin for Unique Input Termination and V T DC-Coupled and AC-Coupled Inputs CML, termination network through a V pin. This feature T allows the device to easily interface to different logic PECL, LVDS, and HSTL standards. A V reference is included for TTL/CMOS Inputs for Select and Reset REF-AC AC-coupled applications. 100KEP-Compatible LVPECL Outputs The /RESET input asynchronously resets the divider. In Parallel Programming Capability the pass-through function (divide by 1) the /RESET Programmable Divider Ratios of 1, 2, 4, 8, and 16 synchronously enables or disables the outputs on the Low-Voltage Operation: 2.5V or 3.3V next falling edge of IN (rising edge of /IN). Output Disable Function 40C to +85C Temperature Range Available in 16-Pin (3 mm x 3 mm) QFN Package Package Type SY89874U Applications 3 mm x 3 mm QFN-16 (M) (Top View) SONET/SDH Line Cards Transponders High-End Multiprocessor Sensors 16 15 14 13 1 12 IN Q0 /Q0 2 11 VT 3 10 VREF-AC Q1 /Q1 4 9 /IN 5 6 7 8 United States Patent No. RE44,134 2018 Microchip Technology Inc. DS20006108B-page 1 S2 S0 NC S1 VCC VCC /RESET GNDSY89874U Functional Block Diagram S2 /RESET ENABLE FF ENABLE Q0 MUX /Q0 MUX Q1 IN DIVIDED R0 /Q1 BY V T 2, 4, 8 R1 or 16 /IN S0 DECODER S1 V REF-AC Typical Performance OC-12 to OC-3 Translator/Divider LVDS LVPECL DIVIDE-BY-4 622MHz 155.5MHz CLOCK-IN CLOCK-OUT 622MHz In IN /IN 155.5MHz Out Q0 /Q0 TRUTH TABLE /RESET S2 S1 S0 Outputs 1 0 X X Reference clock (pass-through) 1100 Reference clock 2 1101 Reference clock 4 1110 Reference clock 8 1111 Reference clock 16 0 1 X X Q = Low, /Q = High clock disable DS20006108B-page 2 2018 Microchip Technology Inc.