TP5322 P-Channel Enhancement-Mode Vertical DMOS FET Features General Description 2.4V Maximum Low Threshold The TP5322 low-threshold Enhancement-mode (normally-off) transistor uses a vertical DMOS structure High Input Impedance and a well-proven silicon-gate manufacturing process. 110 pF Maximum Low Input Capacitance This combination produces a device with the power Fast Switching Speeds handling capabilities of bipolar transistors and the high Low On-Resistance input impedance and positive temperature coefficient Free from Secondary Breakdown inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and Low Input and Output Leakage thermally induced secondary breakdown. Applications Microchips vertical DMOS FETs are ideally suited for a wide range of switching and amplifying applications Logic-Level Interfaces (Ideal for TTL and CMOS) where very low threshold voltage, high breakdown Battery-Operated Systems voltage, high input impedance, low input capacitance, Photovoltaic Drives and fast switching speeds are desired. Analog Switches General Purpose Line Drivers Telecommunication Switches Package Types 3-lead SOT-23 3-lead SOT-89 (Top view) (Top view) DRAIN DRAIN SOURCE SOURCE DRAIN GATE GATE See Table 2-1 and Table 2-2 for pin information. 2020 Microchip Technology Inc. DS20005973A-page 1TP5322 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Drain-to-Source Voltage....................................................................................................................................... BV DSS Drain-to-Gate Voltage .......................................................................................................................................... BV DGS Gate-to-Source Voltage.......................................................................................................................................... 20V Operating Ambient Temperature, T .................................................................................................... 55C to +150C A Storage Temperature, T ...................................................................................................................... 55C to +150C S Notice: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS Electrical Specifications: T = 25C unless otherwise specified. All DC parameters are 100% tested at 25C unless A otherwise stated. Pulse test: 300 s pulse, 2% duty cycle Parameter Sym. Min. Typ. Max. Unit Conditions Drain-to-Source Breakdown Voltage BV 220 V V = 0V, I = 2 mA DSS GS D Gate Threshold Voltage V 1 2.4 V V = V , I = 1 mA GS(th) GS DS D V = V , I = 1 mA GS DS D Change in V with Temperature V 4.5 mV/C GS(th) GS(th) (Note 1) Gate Body Leakage Current I 100 nA V = 20V, V = 0V GSS GS DS V = Maximum rating, DS 10 A V = 0V GS Zero-Gate Voltage Drain Current I V = 0.8 Maximum rating, DSS DS 1 mA V = 0V, T = 125C GS A (Note 1) On-State Drain Current I 0.7 0.95 A V = 10V, V = 25V D(ON) GS DS 10 15 V = 4.5V, I = 100 mA GS D Static Drain-to-Source On-State Resistance R DS(ON) 8 12 V = 10V, I = 200 mA GS D V = 10V, I = 200 mA GS D Change in R with Temperature R 1.7 %/C DS(ON) DS(ON) (Note 1) Note 1: Specification is obtained by characterization and is not 100% tested. DS20005973A-page 2 2020 Microchip Technology Inc.