Product Information

ZL30112LDG1

ZL30112LDG1 electronic component of Microchip

Datasheet
Clock Generators & Support Products Pb Free SLIC/CODEC DPLL
Manufacturer: Microchip
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 4.895 ea
Line Total: USD 4.89

15 - Global Stock
Ships to you between
Thu. 16 May to Wed. 22 May
MOQ: 1  Multiples: 1
Pack Size: 1

 More Buying Options & Price Grid(s)

Availability Price Quantity
15 - WHS 1


Ships to you between Thu. 16 May to Wed. 22 May

MOQ : 1
Multiples : 1

Stock Image

ZL30112LDG1
Microchip

1 : USD 5.0908
10 : USD 5.0661
25 : USD 5.0362
100 : USD 4.9354
490 : USD 4.9354
980 : USD 4.9354

239 - WHS 2


Ships to you between Wed. 22 May to Fri. 24 May

MOQ : 1
Multiples : 1

Stock Image

ZL30112LDG1
Microchip

1 : USD 11.2125
25 : USD 10.212
100 : USD 9.89

Read More Specifications

     
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Additional Infomation About Product

ZL30112 SLIC/CODEC DPLL Data Sheet November 2009 Features Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or Ordering Information 19.44 MHz input ZL30112LDG1 32 Pin QFN* Trays, Bake Provides 2.048 MHz and 8.192 MHz output clocks & Drypack and an 8 kHz framing pulse *Pb Free Matte Tin Automatic entry and exit from freerun mode on -40 C to +85 C reference fail Provides DPLL lock and reference fail indication Description DPLL bandwidth of 29 Hz for all rates of input The ZL30112 SLIC/CODEC DPLL contains a digital references phase-locked loop (DPLL), which provides timing and Less than 0.6 nsec intrinsic jitter on all output pp synchronization for SLIC/CODEC devices. clocks The ZL30112 generates TDM clock and framing 20 MHz external master clock source: clock signals that are phase locked to the input reference. oscillator or crystal It helps ensure system reliability by monitoring its Simple hardware control interface reference for stability and by maintaining stable output clocks during short periods when the Applications reference is unavailable. Synchronizer for POTS SLIC/CODEC Rate convert NTR 8 kHz or GPON physical interface clock to TDM clock REF FAIL LOCK C2o REF C8o DPLL F8ko Reference Monitor Mode Control RST State Machine OSCi Master Clock OSCo Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2007-2009, Zarlink Semiconductor Inc. All Rights Reserved.ZL30112 Data Sheet 1.0 Change Summary Changes from November 2007 Issue. Page, section, figure and table numbers refer to this current issue. Page Item Change 1 Ordering Information Updates to Ordering Information and Package Drawing. 2 Zarlink Semiconductor Inc.

HS Compliance

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits

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