ZL40201 Precision 1:2 LVPECL Fanout Buffer with On-Chip Input Termination Data Sheet April 2014 Ordering Information Features ZL40201LDG1 16 Pin QFN Trays ZL40201LDF1 16 Pin QFN Tape and Reel Inputs/Outputs Matte Tin Accepts differential or single-ended input Package size: 3 x 3 mm o o -40 C to +85 C LVPECL, LVDS, CML, HCSL, LVCMOS On-chip input termination resistors and biasing for Applications AC coupled inputs General purpose clock distribution Two precision LVPECL outputs Low jitter clock trees Operating frequency up to 750 MHz Logic translation Power Clock and data signal restoration Option for 2.5 V or 3.3 V power supply Wired communications: OTN, SONET/SDH, GE, 10 GE, FC and 10G FC Core current consumption of 49 mA PCI Express generation 1/2/3 clock distribution On-chip Low Drop Out (LDO) Regulator for superior Wireless communications power supply rejection High performance microprocessor clock distribution Performance Ultra low additive jitter of 40 fs out0 p out0 n ctrl Termination and Bias vt Buffer clk p clk n out1 p out1 n Figure 1 - Functional Block Diagram 1 Microsemi Corporation Copyright 2014, Microsemi Corporation. All Rights Reserved.ZL40201 Preliminary Data Sheet Table of Contents Features . 1 Inputs/Outputs . 1 Power 1 Performance . 1 Applications . 1 Change Summary . 4 1.0 Package Description 5 2.0 Pin Description . 5 3.0 Functional Description 6 3.1 Clock Inputs . 6 3.2 Clock Outputs 11 3.3 Device Additive Jitter . 14 3.4 Power Supply 15 3.4.1 Sensitivity to power supply noise . 15 3.4.2 Power supply filtering 15 3.4.3 PCB layout considerations 15 4.0 AC and DC Electrical Characteristics . 16 5.0 Performance Characterization . 19 6.0 Typical Behavior 20 7.0 Package Thermal Characteristics 22 8.0 Mechanical Drawing . 23 2 Microsemi Corporation