MT41K128M16JT-125 XIT:K Micron

2Gb: x4, x8, x16 DDR3L SDRAM Description 1.35V DDR3L SDRAM MT41K512M4 64 Meg x 4 x 8 banks MT41K256M8 32 Meg x 8 x 8 banks MT41K128M16 16 Meg x 16 x 8 banks Automatic self refresh (ASR) Description Write leveling The 1.35V DDR3L SDRAM device is a low-voltage ver- Multipurpose register sion of the 1.5V DDR3 SDRAM device. Unless stated Output driver calibration otherwise, the DDR3L SDRAM device meets the func- Options Marking tional and timing specifications listed in the equiva- Configuration lent density standard or automotive DDR3 SDRAM 512 Meg x 4 512M4 data sheet located on www.micron.com. 256 Meg x 8 256M8 Features 128 Meg x 16 128M16 V = V = 1.35V (1.2831.45V) DD DDQ FBGA package (Pb-free) x4, x8 Backward-compatible to V = V = 1.5V 0.075V DD DDQ 78-ball (8mm x 10.5mm) DA Differential bidirectional data strobe Rev. H, M, K 8n-bit prefetch architecture 78-ball FBGA (9mm x 11.5mm) HX Differential clock inputs (CK, CK ) Rev. D 8 internal banks FBGA package (Pb-free) x16 Nominal and dynamic on-die termination (ODT) 96-ball FBGA (9mm x 14mm) HA for data, strobe, and mask signals Rev. D Programmable CAS (READ) latency (CL) 96-ball FBGA (8mm x 14mm) JT Programmable posted CAS additive latency (AL) Rev. K Programmable CAS (WRITE) latency (CWL) Timing cycle time Fixed burst length (BL) of 8 and burst chop (BC) of 4 1.071ns CL = 13 (DDR3-1866) -107 (via the mode register set MRS ) 1.25ns CL = 11 (DDR3-1600) -125 Selectable BC4 or BL8 on-the-fly (OTF) 1.5ns CL = 9 (DDR3-1333) -15E Self refresh mode 1.875ns CL = 7 (DDR3-1066) -187E T of 0C to +95C C Operating temperature 64ms, 8192-cycle refresh at 0C to +85C Commercial (0C T +95C) None C 32ms at +85C to +95C Industrial (40C T +95C) IT C Self refresh temperature (SRT) Revision :D/ :H/ :K/ :M Table 1: Key Timing Parameters t t t t Speed Grade Data Rate (MT/s) Target RCD- RP-CL RCD (ns) RP (ns) CL (ns) 1, 2, 3 -107 1866 13-13-13 13.91 13.91 13.91 1, 2 -125 1600 11-11-11 13.75 13.75 13.75 1 -15E 1333 9-9-9 13.5 13.5 13.5 -187E 1066 7-7-7 13.1 13.1 13.1 1. Backward compatible to 1066, CL = 7 (-187E). Notes: 2. Backward compatible to 1333, CL = 9 (-15E). 3. Backward compatible to 1600, CL = 11 (-107). PDF: 09005aef83ed2952 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 2Gb 1 35V DDR3L.pdf - Rev. I 10/12 EN 2010 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.2Gb: x4, x8, x16 DDR3L SDRAM Description Table 2: Addressing Parameter 512 Meg x 4 256 Meg x 8 128 Meg x 16 Configuration 64 Meg x 4 x 8 banks 32 Meg x 8 x 8 banks 16 Meg x 16 x 8 banks Refresh count 8K 8K 8K Row address 32K A 14:0 32K A 14:0 16K A 13:0 Bank address 8 BA 2:0 8 BA 2:0 8 BA 2:0 Column address 2K A 11, 9:0 1K A 9:0 1K A 9:0 PDF: 09005aef83ed2952 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 2Gb 1 35V DDR3L.pdf - Rev. I 10/12 EN 2010 Micron Technology, Inc. All rights reserved.