Product Information

MT46H32M16LFBF-5 IT:C TR

MT46H32M16LFBF-5 IT:C TR electronic component of Micron

Datasheet
MOBILE DDR 512M 32MX16 FBGA

Manufacturer: Micron
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 5.4458 ea
Line Total: USD 5.4458

1276 - Global Stock
Ships to you between
Thu. 11 Apr to Mon. 15 Apr
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
21 - Global Stock


Ships to you between Fri. 05 Apr to Thu. 11 Apr

MOQ : 1
Multiples : 1
1 : USD 4.7308
10 : USD 4.7308

1417 - Global Stock


Ships to you between
Fri. 12 Apr to Wed. 17 Apr

MOQ : 1
Multiples : 1
1 : USD 9.5775
10 : USD 9.3205
30 : USD 8.874
100 : USD 8.4837

1276 - Global Stock


Ships to you between Thu. 11 Apr to Mon. 15 Apr

MOQ : 1
Multiples : 1
1 : USD 5.4458
10 : USD 5.0353
100 : USD 4.7817
250 : USD 4.7696
500 : USD 4.6489
1000 : USD 4.4074
2000 : USD 4.3108
5000 : USD 4.3108
10000 : USD 4.3108

6790 - Global Stock


Ships to you between Fri. 05 Apr to Thu. 11 Apr

MOQ : 1000
Multiples : 1000
1000 : USD 7.2214

21 - Global Stock


Ships to you between Fri. 05 Apr to Thu. 11 Apr

MOQ : 2
Multiples : 1
2 : USD 5.5492
10 : USD 4.8274

     
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512Mb: x16, x32 Mobile LPDDR SDRAM Features Mobile Low-Power DDR SDRAM MT46H32M16LF 8 Meg x 16 x 4 banks MT46H16M32LF 4 Meg x 32 x 4 banks MT46H16M32LG 4 Meg x 32 x 4 banks Options Marking Features V /V DD DDQ V /V = 1.701.95V DD DDQ 1.8V/1.8V H Bidirectional data strobe per byte of data (DQS) Configuration Internal, pipelined double data rate (DDR) 32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16 architecture two data accesses per clock cycle 16 Meg x 32 (4 Meg x 32 x 4 banks) 16M32 Addressing Differential clock inputs (CK and CK ) JEDEC-standard addressing LF Commands entered on each positive CK edge 1 Reduced page size LG DQS edge-aligned with data for READs center- Plasticgree package aligned with data for WRITEs 2 60-ball VFBGA (8mm x 9mm) BF 4 internal banks for concurrent operation 3 90-ball VFBGA (8mm x 13mm) B5 Data masks (DM) for masking write data one mask Timing cycle time per byte 5ns CL = 3 (200 MHz) -5 Programmable burst lengths (BL): 2, 4, 8, or 16 5.4ns CL = 3 (185 MHz) -54 6ns CL = 3 (166 MHz) -6 Concurrent auto precharge option is supported 7.5ns CL = 3 (133 MHz) -75 Auto refresh and self refresh modes Power 1.8V LVCMOS-compatible inputs Standard I /I None DD2 DD6 Temperature-compensated self refresh (TCSR) Operating temperature range Partial-array self refresh (PASR) Commercial (0 to +70C) None Deep power-down (DPD) Industrial (40C to +85C) IT Automotive (40C to +105C) AT Status read register (SRR) Design revision :C Selectable output drive strength (DS) 1. Contact factory for availability. Clock stop capability Notes: 2. Only available for x16 configuration. 64ms refresh, 32ms for automotive temperature 3. Only available for x32 configuration. Table 1: Key Timing Parameters (CL = 3) Speed Grade Clock Rate Access Time -5 200 MHz 5.0ns -54 185 MHz 5.0ns -6 166 MHz 5.0ns -75 133 MHz 6.0ns PDF: 09005aef83dd2b3e Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 t67m 512mb mobile lpddr.pdf - Rev. I 01/14 EN 2009 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.512Mb: x16, x32 Mobile LPDDR SDRAM Features Table 2: Configuration Addressing Reduced Page Size Architecture 32 Meg x 16 16 Meg x 32 16 Meg x 32 Configuration 8 Meg x 16 x 4 banks 4 Meg x 32 x 4 banks 4 Meg x 32 x 4 banks Refresh count 8K 8K 8K Row addressing 8K A 12:0 8K A 12:0 16K A 13:0 Column addressing 1K A 9:0 512 A 8:0 256 A 7:0 Figure 1: 512Mb Mobile LPDDR Part Numbering MT 46 H 32M16 LF BF -6 IT :C Micron Technology Design Revision :C = Third generation Product Family 46 = Mobile LPDDR Operating Temperature Blank = Commercial (0C to +70C) Operating Voltage IT = Industrial (40C to +85C) H = 1.8/1.8V AT = Automotive (40C to +105C) Configuration Power 32 Meg x 16 Blank = Standard I /I DD2 DD6 16 Meg x 32 Cycle Time (CL = 3) t Addressing -5 = 5ns CK t LF = JEDEC-standard -54 = 5.4ns CK t LG = Reduced page size -6 = 6ns CK t -75 = 7.5ns CK Package Codes BF = 60-ball (8mm x 9mm) VFBGA, green B5 = 90-ball (8mm x 13mm) VFBGA, green FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Microns FBGA part marking decoder is available at www.micron.com/decoder. PDF: 09005aef83dd2b3e Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 t67m 512mb mobile lpddr.pdf - Rev. I 01/14 EN 2009 Micron Technology, Inc. All rights reserved.

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:
EL9
Elpida Memory
ELPIDA MEMORY INC
IE6
MI9
MICRON SEMICONDUCTOR
Micron Tech
MICRON TECHNOLOGY
Micron Technology Inc
Micron Technology Inc.
NU9
Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC. (VA)

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