256Mb: x4, x8, x16 DDR SDRAM Features Double Data Rate (DDR) SDRAM MT46V64M4 16 Meg x 4 x 4 banks MT46V32M8 8 Meg x 8 x 4 banks MT46V16M16 4 Meg x 16 x 4 banks Options Marking Features V = 2.5V 0.2V V = 2.5V 0.2V Configuration DD DDQ 1 V = 2.6V 0.1V V = 2.6V 0.1V (DDR400) 64 Meg x 4 (16 Meg x 4 x 4 banks) 64M4 DD DDQ Bidirectional data strobe (DQS) transmitted/ 32 Meg x 8 (8 Meg x 8 x 4 banks) 32M8 received with data, that is, source-synchronous data 16 Meg x 16 (4 Meg x 16 x 4 banks) 16M16 capture (x16 has two one per byte) Plastic package OCPL Internal, pipelined double data rate (DDR) 66-pin TSOP TG architecture two data accesses per clock cycle 66-pin TSOP (Pb-free) P Differential clock inputs (CK and CK ) Plastic package Commands entered on each positive CK edge 60-ball FBGA (8mm x 12.5mm) CV DQS edge-aligned with data for READs center- 60-ball FBGA (8mm x 12.5mm) CY aligned with data for WRITEs (Pb-free) DLL to align DQ and DQS transitions with CK Timing cycle time 3 Four internal banks for concurrent operation 5ns CL = 3 (DDR400) -5B 2 Data mask (DM) for masking write data 6ns CL = 2.5 (DDR333) FBGA only -6 2 (x16 has two one per byte) 6ns CL = 2.5 (DDR333) TSOP only -6T Programmable burst lengths (BL): 2, 4, or 8 Self refresh Auto refresh Standard None 64ms, 8192-cycle Low-power self refresh L Longer-lead TSOP for improved reliability (OCPL) Temperature rating 2.5V I/O (SSTL 2-compatible) Commercial (0 C to +70 C) None Concurrent auto precharge option supported Industrial (40 C to +85 C) IT t t t RAS lockout supported ( RAP = RCD) Revision 4 x4, x8, x16 :K x4, x8, x16 :M Notes: 1. DDR400 devices operating at < DDR333 conditions can use V /V = 2.5V +0.2V. DD DDQ 2. Available only on Revision K. 3. Available only on Revision M. 4. Not recommended for new designs. Table 1: Key Timing Parameters CL = CAS (READ) latency MIN clock rate with 50% duty cycle at CL = 2 (-75E, -75Z), CL = 2.5 (-6, -6T, -75), and CL = 3 (-5B) Clock Rate (MHz) Access DQSDQ Speed Grade CL = 2 CL = 2.5 CL = 3 Data-Out Window Window Skew -5B 133 167 200 1.6ns 0.70ns 0.40ns -6 133 167 n/a 2.1ns 0.70ns 0.40ns 6T 133 167 n/a 2.0ns 0.70ns 0.45ns -75E/-75Z 133 133 n/a 2.5ns 0.75ns 0.50ns -75 100 133 n/a 2.5ns 0.75ns 0.50ns PDF: 09005aef80768abb/Source: 09005aef82a95a3a Micron Technology, Inc., reserves the right to change products or specifications without notice. 256Mb DDR x4x8x16 D1.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/15 EN 1 2003 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 256Mb: x4, x8, x16 DDR SDRAM Features Table 2: Addressing Parameter 64 Meg x 4 32 Meg x 8 16 Meg x 16 Configuration 16 Meg x 4 x 4 banks 8 Meg x 8 x 4 banks 4 Meg x 16 x 4 banks Refresh count 8K 8K 8K Row address 8K (A 12:0 ) 8K (A 12:0 ) 8K (A 12:0 ) Bank address 4 (BA 1:0 ) 4 (BA 1:0 ) 4 (BA 1:0 ) Column address 2K (A 9:0 , A11) 1K (A 9:0 ) 512 (A 8:0 ) Table 3: Speed Grade Compatibility Marking PC3200 (3-3-3) PC2700 (2.5-3-3) PC2100 (2-2-2) PC2100 (2-3-3) PC2100 (2.5-3-3) PC1600(2-2-2) 1 Yes Yes Yes Yes Yes Yes -5B Yes Yes Yes Yes Yes -6 Yes Yes Yes Yes Yes -6T Yes Yes Yes Yes -75E Yes Yes Yes -75Z Yes Yes -75 -5B -6/-6T -75E -75Z -75 -75 Notes: 1. The -5B device is backward compatible with all slower speed grades. The voltage range of -5B device operating at slower speed grades is V = V = 2.5V 0.2V. DD DDQ Figure 1: 256Mb DDR SDRAM Part Numbers Example Part Number: MT46V16M16P-6T:M : - Sp. MT46V Configuration Package Speed Temp. Revision Op. Configuration Revision 64 Meg x 4 64M4 x4, x8, x16 :K 32 Meg x 8 32M8 x4, x8, x16 :M 16 Meg x 16 16M16 Package Operating Temp. 400-mil TSOP TG Commercial 400-mil TSOP (Pb-free) P IT Industrial 8mm x 12.5mm FBGA CV 8mm x 12.5mm FBGA (Pb-free) CY Special Options Standard L Low power Speed Grade t -5B CK = 5ns, CL = 3 t -6 CK = 6ns, CL = 2.5 t -6T CK = 6ns, CL = 2.5 PDF: 09005aef80768abb/Source: 09005aef82a95a3a Micron Technology, Inc., reserves the right to change products or specifications without notice. 256Mb DDR x4x8x16 D1.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 3/15 EN 2 2003 Micron Technology, Inc. All rights reserved.