Product Information

MT48LC4M32B2P-6A IT

MT48LC4M32B2P-6A IT electronic component of Micron

Datasheet
SDRAM, 128MBIT, 166MHZ, 86TSOP
Manufacturer: Micron
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 14.0725 ea
Line Total: USD 14.07

0 - Global Stock
MOQ: 1  Multiples: 1
Pack Size: 1

 More Buying Options & Price Grid(s)

Availability Price Quantity
0 - WHS 1


Ships to you between Thu. 23 May to Wed. 29 May

MOQ : 1
Multiples : 1
1 : USD 14.0725
10 : USD 12.0978

Read More Specifications

     
Manufacturer
Product Category
Memory Type
Dram Memory Configuration
Access Time
Page Size
No Of Pins
Memory Case Style
Operating Temperature Min
Operating Temperature Max
Ic Interface Type
Packaging
Msl
Svhc
Operating Temperature Range
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Additional Infomation About Product

128Mb: x32 SDRAM Features SDR SDRAM MT48LC4M32B2 1 Meg x 32 x 4 Banks Options Marking Features Configuration PC100-compliant 4 Meg x 32 (1 Meg x 32 x 4 banks) 4M32B2 Fully synchronous all signals registered on positive 1 Package OCPL edge of system clock 86-pin TSOP II (400 mil) TG Internal pipelined operation column address can 86-pin TSOP II (400 mil) Pb-free P be changed every clock cycle 90-ball VFBGA (8mm x 13mm) F5 Internal banks for hiding row access/precharge 90-ball VFBGA (8mm x 13mm) Pb- B5 Programmable burst lengths: 1, 2, 4, 8, or full page free Auto precharge, includes concurrent auto precharge Timing (cycle time) and auto refresh modes 3 6ns (166 MHz) -6A Self refresh mode (not available on AT devices) 2 6ns (166 MHz) -6 Auto refresh 2 7ns (143 MHz) -7 64ms, 4096-cycle refresh (commercial and Revision :G/:L industrial) Operating temperature range 16ms, 4096-cycle refresh (automotive) Commercial (0C to +70C) None LVTTL-compatible inputs and outputs Industrial (40C to +85C) IT Single 3.3V 0.3V power supply 4 Automotive (40C to +105C) AT Supports CAS latency (CL) of 1, 2, and 3 1. Off-center parting line. Notes: 2. Available only on Revision G. 3. Available only on Revision L. 4. Contact Micron for availability. Table 1: Key Timing Parameters CL = CAS (READ) latency Clock t t t t Speed Grade Frequency (MHz) Target RCD- RP-CL RCD (ns) RP (ns) CL (ns) -6 167 3-3-3 18 18 18 -6A 167 3-3-3 18 18 18 -7 143 3-3-3 15 15 15 PDF: 09005aef80872800 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 128mb x32 sdram.pdf - Rev. R 10/12 EN 2001 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.128Mb: x32 SDRAM Features Table 2: Address Table Parameter 4 Meg x 32 Configuration 1 Meg x 32 x 4 banks Refresh count 4K Row addressing 4K A 11:0 Bank addressing 4 BA 1:0 Column addressing 256 A 7:0 Table 3: 128Mb (x32) SDR Part Numbering Part Numbers Architecture MT48LC4M32B2TG 4 Meg x 32 MT48LC4M32B2P 4 Meg x 32 1 MT48LC4M32B2F5 4 Meg x 32 1 MT48LC4M32B2B5 4 Meg x 32 Note: 1. FBGA Device Decoder: www.micron.com/decoder. PDF: 09005aef80872800 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 128mb x32 sdram.pdf - Rev. R 10/12 EN 2001 Micron Technology, Inc. All rights reserved.

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