RFM products are now Murata products. TRC105 Product Overview 300-510 MHz TRC105 is a single chip, multi-channel, low power UHF transceiver. It is RF Transceiver designed for low cost, high volume, two-way short range wireless applica- tions in the 300 to 510 MHz frequency range. The TRC105 is FCC & ETSI certifiable. All critical RF and base-band functions are integrated in the TRC105, minimizing external component count and simplifying and speeding design-ins. A microcontroller, RF SAW filter, 12.8 MHz crystal and a few pas- sive components are all that is needed to create a complete, robust radio function. The TRC105 incorporates a set of low-power states to reduce cur- rent consumption and extend battery life. The small size and low power con- sumption of the TRC105 make it ideal for a wide variety of short range radio applications. The TRC105 complies with Directive 2002/95/EC (RoHS). Pb Key Features Modulation: FSK or OOK with frequency hop- Integrated RSSI ping spread spectrum capability Integrated crystal oscillator Frequency range: 300 to 510 MHz Host processor interrupt pins High sensitivity: -112 dBm in circuit Programmable data rate High data rate: up to 200 kb/s External wake-up event inputs Low receiver current: 2.7 mA typical Integrated packet CRC error detection Low sleep current: 0.1 A typical Integrated DC-balanced data scrambling Up to +13 dBm in-circuit transmit power Integrated Manchester encoding/decoding Operating supply voltage: 2.1 to 3.6 V Interrupt signal mapping function Programmable preamble Support for multiple channels Programmable packet start pattern Four power-saving modes Integrated RF, PLL, IF and base-band circuitry Low external component count Integrated data & clock recovery TQFN-32 SMT package Programmable RF output power Standard 13 inch reel, 3K pieces PLL lock output Applications Transmit/receive FIFO size programmable up to 64 bytes Active RFID tags Continuous, buffered and packet data modes Automated meter reading Packet address recognition Home & industrial automation Packet handling features: Security systems Fixed or variable packet length Two-way remote keyless entry Packet filtering Automobile immobilizers Packet formatting Sports performance monitoring Standard SPI interface Wireless toys TTL/CMOS compatible I/O pins Medical equipment Programmable clock output frequency Low power two-way telemetry systems Low Battery Detection Wireless mesh sensor networks Low cost 12.8 MHz crystal reference Wireless modules 1 of 67 2010-2015 by Murata Electronics N.A., Inc. TRC105 (R) 04/28/15 www.murata.comTable of Contents 1.0 Pin Configuration ..................................................................................................................................... 4 1.1 Pin Description .................................................................................................................................. 4 2.0 Functional Description ............................................................................................................................. 5 2.1 RF Port .............................................................................................................................................. 7 2.2 Transmitter ........................................................................................................................................ 7 2.3 Receiver ............................................................................................................................................ 8 2.4 Crystal Oscillator ............................................................................................................................... 9 2.5 Frequency Synthesizer ................................................................................................................... 10 2.6 PLL Loop Filter ................................................................................................................................ 11 3.0 Operating Modes ................................................................................................................................... 11 3.1 Receiving in Continuous Data Mode ............................................................................................... 12 3.2 Continuous Mode Data and Clock Recovery .................................................................................. 14 3.3 Continuous Mode Start Pattern Detect ........................................................................................... 14 3.4 RSSI ................................................................................................................................................ 15 3.5 Receiving in Buffered Data Mode ................................................................................................... 15 3.6 Transmitting in Continuous or Buffered Data Modes ...................................................................... 17 3.7 IRQ0 and IRQ1 Mapping................................................................................................................. 18 3.8 Buffered Clock Output ..................................................................................................................... 19 3.9 Packet Data Mode ........................................................................................................................... 19 3.9.1 Fixed Length Packet Mode .................................................................................................... 19 3.9.2 Variable Length Packet Mode ............................................................................................... 20 3.9.3 Extended Variable Length Packet Mode ............................................................................... 20 3.9.4 Packet Payload Processing in Transmit and Receive ........................................................... 22 3.9.5 Packet Filtering ...................................................................................................................... 23 3.9.6 Cyclic Redundancy Check ..................................................................................................... 23 3.9.7 Manchester Encoding ............................................................................................................ 24 3.9.8 DC-Balanced Scrambling ...................................................................................................... 25 3.10 SPI Configuration Interface ........................................................................................................... 25 3.11 SPI Data FIFO Interface................................................................................................................ 27 4.0 Configuration Register Memory Map ..................................................................................................... 29 4.1 Main Configuration Registers (MCFG) ............................................................................................ 30 4.2 Interrupt Configuration Registers (IRQCFG)................................................................................... 33 4.3 Receiver Configuration Registers (RXCFG) ................................................................................... 35 4.4 Start Pattern Configuration Registers (SYNCFG) ........................................................................... 38 4.5 Transmitter Configuration Registers (TXCFG) ............................................................................... 38 4.6 Oscillator Configuration Register (OSCFG) .................................................................................... 39 4.7 Packet Handler Configuration Registers (PKTCFG) ....................................................................... 39 4.8 Page Configuration Register (PGCFG) ........................................................................................... 40 4.9 Low Battery Configuration Registers (LBCFG) ............................................................................... 41 5.0 Electrical Characteristics ....................................................................................................................... 42 5.1 DC Electrical Characteristics .......................................................................................................... 42 5.2 AC Electrical Characteristics ........................................................................................................... 43 6.0 TRC105 Design-In Steps ....................................................................................................................... 45 6.1 Determining Frequency Specific Hardware Component Values..................................................... 45 6.1.1 SAW Filters and Related Component Values ....................................................................... 45 6.1.2 Voltage Controlled Oscillator Component Values ................................................................. 46 2 of 67 2010-2015 by Murata Electronics N.A., Inc. TRC105 (R) 04/28/15 www.murata.com